ZUSBOPTSC01ZAC datasheet(192/402 Pages) ZILOG

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I2C Master/Slave Controller

P R E L I M I N A R Y

PS024604-1005

Z8 Encore!® Motor Control Flash MCUs

Product Specification

170

Master Arbitration

If a master loses arbitration during the address byte, it releases the SDA line, switches to

SLAVE mode and monitors the address to determine if it is selected as a slave. If a master

loses arbitration during the transmission of a data byte, it releases the SDA line and waits

for the next STOP or START condition.

The master detects a loss of arbitration when a 1 is transmitted but a 0 is received from the

bus in the same bit-time. This loss occurs if more than one master is simultaneously

accessing the bus. Loss of arbitration can occur during the address phase (two or more

masters accessing different slaves) or during the data phase, when the masters are attempt-

ing to write different data to the same slave.

When a master loses arbitration, the software is informed by means of the Arbitration Lost

interrupt. The software can repeat the same transaction at a later time.

A special case can occur when a slave transaction starts just before the software attempts

to start a new master transaction by setting the START bit. In this case, the state machine

enters its slave states before the START bit is set, and as a result, the I2C controller will not

arbitrate. If a slave address match occurs and the I2C controller receives/transmits data, the

START

bit is cleared and an Arbitration Lost interrupt is asserted. The software can mini-

mize the chance of this instance occurring by checking the BUSY bit in the I2CSTATE

Arbitration Lost interrupt will not occur, and the START bit will not be cleared. The I2C

controller will initiate the master transaction after the I2C bus is no longer busy.

Master Address-Only Transactions

It is sometimes preferable to perform an address-only transaction to determine if a particu-

lar slave device is able to respond. This transaction can be performed by monitoring the

ACKV

bit in the I2CSTATE Register after the address has been written to the I2CDATA

I2CSTATE Register determines if the slave is able to communicate. The STOP bit must be

set in the I2CCTL Register to terminate the transaction without transferring data. For a 10-

bit slave address, if the first address byte is acknowledged, the second address byte should

also be sent to determine if the preferred slave is responding.

Another approach is to set both the STOP and START bits (for sending a 7-bit address).

After both bits have cleared (7-bit address has been sent and transaction is complete), the

ACK

bit can be read to determine if the slave has acknowledged. For a 10-bit slave, set the

STOP

bit after the second TDRE interrupt (which indicates that the second address byte is

being sent).

Master Transaction Diagrams

In the following transaction diagrams, the shaded regions indicate the data that is trans-

ferred from the master to the slave, and the unshaded regions indicate the data that is trans-

ferred from the slave to the master. The transaction field labels are defined as follows:

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