ZUSBOPTSC01ZAC datasheet(196/402 Pages) ZILOG

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I2C Master/Slave Controller

P R E L I M I N A R Y

PS024604-1005

Z8 Encore!® Motor Control Flash MCUs

Product Specification

174

16. The I2C slave sends an Acknowledge by pulling the SDA signal Low during the next

high period of SCL. The I2C controller sets the ACK bit in the I2C Status Register.

If the slave does not acknowledge, refer to the second paragraph of Step 11.

17. The I2C controller shifts the data out by the SDA signal. After the first bit is sent, the

transmit interrupt asserts.

18. If more bytes remain to be sent, return to Step 14.

19. The software responds by asserting the STOP bit of the I2C Control Register.

20. The I2C controller completes transmission of the data on the SDA signal.

21. The I2C controller sends a STOP condition to the I2C bus.

If the slave responds with a Not Acknowledge during the transfer, the I2C controller

asserts the NCKI bit, sets the ACKV bit, clears the ACK bit in the I2C State Register, and

halts. The software terminates the transaction by setting either the STOP bit (end transac-

tion) or the START bit (end this transaction, start a new one). The Transmit Data Register

is flushed automatically.

Master Read Transaction with a 7-Bit Address

Figure 30 illustrates the data transfer format for a read operation to a 7-bit addressed slave.

The procedure for a master Read operation to a 7-bit addressed slave is as follows:

1. The software initializes the MODE field in the I2C Mode Register for MASTER/

SLAVE mode with 7- or 10-bit addressing (the I2C bus protocol allows the mixing of

slave address types). The MODE field selects the address width for this mode when

addressed as a slave (but not for the remote slave). The software asserts the IEN bit in

the I2C Control Register.

2. The software writes the I2C Data Register with a 7-bit slave address, plus the Read bit

(which is set to 1).

3. The software asserts the START bit of the I2C Control Register.

4. If this operation is a single-byte transfer, the software asserts the NAK bit of the I2C

Control Register so that after the first byte of data has been read by the I2C controller,

a Not Acknowledge instruction is sent to the I2C slave.

5. The I2C controller sends a START condition.

6. The I2C controller sends the address and Read bit out via the SDA signal.

Slave Address

R = 1

Data

P/S

Figure 30. Data Transfer Format—Master Read Transaction with a 7-Bit Address

Note:

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