ZUSBOPTSC01ZAC datasheet(198/402 Pages) ZILOG

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I2C Master/Slave Controller

P R E L I M I N A R Y

PS024604-1005

Z8 Encore!® Motor Control Flash MCUs

Product Specification

176

3. The software asserts the START bit of the I2C Control Register.

4. The I2C controller sends a START condition.

5. The I2C controller loads the I2C Shift Register with the contents of the I2C Data Reg-

ister.

6. After the first bit has been shifted out, a transmit interrupt is asserted.

7. The software responds by writing the least significant eight bits of address to the I2C

Data Register.

8. The I2C controller completes shifting of the first address byte.

9. The I2C slave sends an Acknowledge by pulling the SDA signal Low during the next

high period of SCL.

If the slave does not acknowledge the address byte, the I2C controller sets the NCKI

bit in the I2C Status Register, sets the ACKV bit and clears the ACK bit in the I2C State

bit and clearing the TXI bit. The I2C controller flushes the Transmit Data Register,

sends the STOP condition on the bus and clears the STOP and NCKI bits. The transac-

tion is complete, and the following steps can be ignored.

10. The I2C controller loads the I2C Shift Register with the contents of the I2C Data Reg-

ister (the lower byte of the 10-bit address).

11. The I2C controller shifts out the next eight bits of the address. After the first bit shifts,

the I2C controller generates a transmit interrupt.

12. The software responds by setting the START bit of the I2C Control Register to generate

a repeated START condition.

13. The software writes 11110b, followed by the 2-bit slave address and a 1 (Read) to the

I2C Data Register.

14. If the user chooses to read only one byte, the software responds by setting the NAK bit

of the I2C Control Register.

15. After the I2C controller shifts out the address bits listed in Step 9 (the second address

transfer), the I2C slave sends an Acknowledge by pulling the SDA signal Low during

the next High period of SCL.

If the slave does not acknowledge the address byte, the I2C controller sets the NCKI

bit in the I2C Status Register, sets the ACKV bit, and clears the ACK bit in the I2C State

bit and clearing the TXI bit. The I2C controller flushes the Transmit Data Register,

sends the STOP condition on the bus, and clears the STOP and NCKI bits. The transac-

tion is complete, and the following steps can be ignored.

16. The I2C controller sends a repeated START condition.

ZUSBOPTSC01ZAC 数据表(PDF) 198 Page - Zilog, Inc.

ZUSBOPTSC01ZAC 数据表(HTML) 198 Page - Zilog, Inc.

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