ZUSBOPTSC01ZAC datasheet(202/402 Pages) ZILOG

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I2C Master/Slave Controller

P R E L I M I N A R Y

PS024604-1005

Z8 Encore!® Motor Control Flash MCUs

Product Specification

180

Slave Receive Transaction with 10-Bit Address

The data transfer format for writing data from a master to a slave with 10-bit addressing is

shown in Figure 33. The procedure that follows describes the I2C Master/Slave Controller

operating as a slave in 10-bit addressing mode and receiving data from the bus master.

1. The software configures the controller for operation as a slave in 10-bit addressing

mode, as follows.

a. Initialize the MODE field in the I2CMODE Register for either SLAVE ONLY

mode or MASTER/SLAVE mode with 10-bit addressing.

b. Optionally set the GCE bit.

c. Initialize the SLA[7:0] bits in the I2CSLVAD Register and the SLA[9:8] bits in

the I2CMODE Register.

d. Set IEN = 1 in the I2CCTL Register. Set NAK = 0 in the I2C Control Register.

2. The master initiates a transfer, sending the first address byte. The I2C controller recog-

nizes the start of a 10-bit address with a match to SLA[9:8] and detects the R/W bit =

0 (a Write from the master to the slave). The I2C controller acknowledges, indicating

it is available to accept the transaction.

3. The master sends the second address byte. The SLAVE mode I2C controller detects an

address match between the second address byte and SLA[7:0]. The SAM bit in the

I2CISTAT Register is set to 1, thereby causing an interrupt. The RD bit is cleared to 0,

indicating a Write to the slave. The I2C controller acknowledges, indicating it is avail-

able to accept the data.

4. The software responds to the interrupt by reading the I2CISTAT Register, which clears

the SAM bit. Because RD = 0, no immediate action is taken by the software until the

first byte of data is received. If the software is only able to accept a single byte, it sets

the NAK bit in the I2CCTL Register.

5. The master detects the Acknowledge and sends the first byte of data.

6. The I2C controller receives the first byte and responds with Acknowledge or Not

Acknowledge, depending on the state of the NAK bit in the I2CCTL Register. The I2C

controller generates the receive data interrupt by setting the RDRF bit in the I2CISTAT

Slave Address

1st Byte

W=0

Slave Address

2nd Byte

Data

A/A

P/S

Figure 33. Data Transfer Format—Slave Receive Transaction with 10-Bit Address

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