ZUSBOPTSC01ZAC datasheet(204/402 Pages) ZILOG

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I2C Master/Slave Controller

P R E L I M I N A R Y

PS024604-1005

Z8 Encore!® Motor Control Flash MCUs

Product Specification

182

5. After the first bit of the first data byte has been transferred, the I2C controller sets the

TDRE

bit, which asserts the transmit data interrupt.

6. The software responds to the transmit data interrupt (TDRE = 1) by loading the next

data byte into the I2CDATA Register, which clears TDRE.

7. After the data byte has been received by the master, the master transmits an Acknowl-

edge instruction (or Not Acknowledge instruction if this byte is the final data byte).

8. The bus cycles through steps 5 to 7 until the final byte has been transferred. If the soft-

ware has not yet loaded the next data byte when the master brings SCL Low to trans-

fer the most significant data bit, the slave I2C controller holds SCL Low until the data

slave, the I2C controller sets the NCKI bit in the I2CISTAT Register, causing the Not

Acknowledge interrupt to be generated.

9. The software responds to the Not Acknowledge interrupt by clearing the TXI bit in the

I2CCTL Register and by asserting the FLUSH bit of the I2CCTL Register to empty the

data register.

10. When the master has completed the final acknowledge cycle, it asserts a STOP or

RESTART

condition on the bus.

11. The slave I2C controller asserts the STOP/RESTART interrupt (set SPRS bit in

I2CISTAT Register).

12. The software responds to the STOP/RESTART interrupt by reading the I2CISTAT Reg-

ister, which clears the SPRS bit.

Slave Transmit Transaction with 10-Bit Address

The data transfer format for a master reading data from a slave with 10-bit addressing is

shown in Figure 35. The following procedure describes the I2C Master/Slave Controller

operating as a slave in 10-bit addressing mode, transmitting data to the bus master.

1. The software configures the controller for operation as a slave in 10-bit addressing

mode.

a. Initialize the MODE field in the I2C Mode Register for either SLAVE ONLY mode

or MASTER/SLAVE mode with 10-bit addressing.

b. Optionally set the GCE bit.

c. Initialize the SLA[7:0] bits in the I2CSLVAD Register and SLA[9:8] in the

I2CMODE Register.

S Slave Address

1st Byte

W = 0 A Slave Address

2nd Byte

S Slave Address

1st Byte

R = 1 A Data AData A

Figure 35. Data Transfer Format—Slave Transmit Transaction with 10-Bit Address

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