ZUSBOPTSC01ZAC datasheet(203/402 Pages) ZILOG

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PS024604-1005

P R E L I M I N A R Y

Slave Transactions

Z8FMC16100 Series Flash MCU

Product Specification

181

7. The software responds by reading the I2CISTAT Register, finding the RDRF bit = 1,

and then reading the I2CDATA Register, which clears the RDRF bit. If the software can

accept only one more data byte, it sets the NAK bit in the I2CCTL Register.

8. The master and slave loops through steps 5 to 7 until the master detects a Not

Acknowledge instruction or runs out of data to send.

9. The master sends the STOP or RESTART signal on the bus. Either of these signals can

cause the I2C controller to assert the STOP interrupt (the STOP bit = 1 in the

I2CISTAT Register). Because the slave received data from the master, the software

takes no action in response to the STOP interrupt other than reading the I2CISTAT

Slave Transmit Transaction with 7-bit Address

The data transfer format for a master reading data from a slave in 7-bit address mode is

shown in Figure 37. The procedure that follows describes the I2C Master/Slave Controller

operating as a slave in 7-bit addressing mode and transmitting data to the bus master.

1. The software configures the controller for operation as a slave in 7-bit addressing

mode, as follows.

a. Initialize the MODE field in the I2C Mode Register for either SLAVE ONLY mode

or MASTER/SLAVE mode with 7-bit addressing.

b. Optionally set the GCE bit.

c. Initialize the SLA[6:0] bits in the I2C Slave Address Register.

d. Set IEN = 1 in the I2C Control Register. Set NAK = 0 in the I2C Control Register.

2. The master initiates a transfer, sending the address byte. The SLAVE mode I2C con-

troller finds an address match and detects that the R/W bit = 1 (read by the master

from the slave). The I2C controller acknowledges, indicating that it is ready to accept

the transaction. The SAM bit in the I2CISTAT Register is set to 1, causing an interrupt.

The RD bit is set to 1, indicating a Read from the slave.

3. The software responds to the interrupt by reading the I2CISTAT Register, thereby

clearing the SAM bit. Because RD = 1, the software responds by loading the first data

byte into the I2CDATA Register. The software sets the TXI bit in the I2CCTL Register

to enable transmit interrupts. When the master initiates the data transfer, the I2C con-

troller holds SCL Low until the software has written the first data byte to the

I2CDATA Register.

4. SCL is released and the first data byte is shifted out.

Slave Address

R = 1

Data

P/S

Figure 34. Data Transfer Format—Slave Transmit Transaction with 7-bit Address

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