ZUSBOPTSC01ZAC datasheet(206/402 Pages) ZILOG

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I2C Master/Slave Controller

P R E L I M I N A R Y

PS024604-1005

Z8 Encore!® Motor Control Flash MCUs

Product Specification

184

12. The software responds to the NAK interrupt by clearing the TXI bit in the I2CCTL

13. When the master has completed the Acknowledge cycle of the last transfer, it asserts a

STOP

or RESTART condition on the bus.

14. The slave I2C controller asserts the STOP/RESTART interrupt (sets the SPRS bit in the

I2CISTAT Register).

15. The software responds to the STOP interrupt by reading the I2CISTAT Register and

clearing the SPRS bit.

I2C Data Register

The I2C Data Register, shown in Table 92, contains the data that is to be loaded into the

Shift Register to transmit onto the I2C bus. This register also contains data that is loaded

from the Shift Register after it is received from the I2C bus. The I2C Shift Register is not

accessible in the Register File address space, but is used only to buffer incoming and out-

going data.

Writes by the software to the I2CDATA Register are blocked if a slave Write transaction is

underway (the I2C controller is in SLAVE mode, and data is being received).

I2C Interrupt Status Register

The read-only I2C Interrupt Status Register, shown in Table 93, indicates the cause of any

current I2C interrupt and provides status of the I2C controller

. When an interrupt occurs,

one or more of the TDRE, RDRF, SAM, ARBLST, SPRS or NCKI bits is set. The GCA and

bits do not generate an interrupt but rather provide status associated with the

SAM

bit interrupt.

Table 92. I2C Data Register (I2CDATA)

BITS

FIELD

DATA

RESET

R/W

ADDR

F50H

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