ZUSBOPTSC01ZAC datasheet(207/402 Pages) ZILOG

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PS024604-1005

P R E L I M I N A R Y

I2C Interrupt Status Register

Z8FMC16100 Series Flash MCU

Product Specification

185

TDRE—Transmit Data Register Empty

When the I2C Controller is enabled, this bit is 1 when the I2C Data register is empty.

When set, this bit causes the I2C Controller to generate an interrupt, except when the I2C

Controller is shifting in data during the reception of a byte or when shifting an address and

the RD bit is set. This bit clears by writing to the I2CDATA register.

RDRF—Receive Data Register Full

This bit is set = 1 when the I2C Controller is enabled and the I2C Controller has received a

byte of data. When asserted, this bit causes the I2C Controller to generate an interrupt.

This bit clears by reading the I2CDATA register.

SAM—Slave Address Match

This bit is set = 1 if the I2C Controller is enabled in Slave mode and an address is received

which matches the unique Slave address or General Call Address (if enabled by the GCE

bit in the I2C Mode register). In 10-bit addressing mode, this bit is not set until a match is

achieved on both address bytes. When this bit is set, the RD and GCA bits are also valid.

This bit clears by reading the I2CISTAT register.

GCA—General Call Address

This bit is set in Slave mode when the General Call Address or START byte is recognized

(in either 7 or 10 bit Slave mode). The GCE bit in the I2C Mode register must be set to

enable recognition of the General Call Address and START byte. This bit clears when IEN

= 0 and is updated following the first address byte of each Slave mode transaction. A Gen-

eral Call Address is distinguished from a START byte by the value of the RD bit (RD = 0

for General Call Address, 1 for START byte).

RD—Read

This bit indicates the direction of transfer of the data. It is set when the Master is reading

data from the Slave. This bit matches the least-significant bit of the address byte after the

START condition occurs (for both Master and Slave modes). This bit clears when IEN = 0

and is updated following the first address byte of each transaction.

ARBLST—Arbitration Lost

This bit is set when the I2C Controller is enabled in Master mode and loses arbitration

(outputs a 1 on SDA and receives a 0 on SDA). The ARBLST bit clears when the

I2CISTAT register is read.

Table 93. I2C Interrupt Status Register (I2CISTAT)

BITS

FIELD

TDRE

RDRF

SAM

GCA

ARBLST

SPRS

NCKI

RESET

R/W

ADDR

F51H

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