ZUSBOPTSC01ZAC datasheet(211/402 Pages) ZILOG

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PS024604-1005

P R E L I M I N A R Y

I2C State Register

Z8FMC16100 Series Flash MCU

Product Specification

189

ACKV—ACK Valid

This bit is set if sending data (Master or Slave) and the ACK bit in this register is valid for

the byte just transmitted. This bit can be monitored if it is appropriate for software to ver-

ify the ACK value before writing the next byte to be sent. To operate in this mode, the data

This bit clears when transmission of the next byte begins or the transaction is ended by a

STOP or RESTART condition.

ACK—Acknowledge

This bit indicates the status of the Acknowledge for the last byte transmitted or received.

This bit is set for an Acknowledge and cleared for a Not Acknowledge condition.

AS—Address State

This bit is active High while the address is being transferred on the I2C bus.

DS—Data State

This bit is active high while the data is being transferred on the I2C bus.

10B—This bit indicates whether a 10 or 7-bit address is being transmitted when operating

as a Master. After the START bit is set, if the five most-significant bits of the address are

11110B, this bit is set. When set, it is reset once the address has been sent.

RSTR—RESTART

This bit is updated each time a STOP or RESTART interrupt occurs (SPRS bit set in

I2CISTAT register).

0 = Stop condition

1 = Restart condition

SCLOUT—Serial Clock Output

Current value of Serial Clock being output onto the bus. The actual values of the SCL and

SDA signals on the I2C bus can be observed via the GPIO Input register.

BUSY—I2C Bus Busy

0 = No activity on the I2C Bus.

1 = A transaction is underway on the I2C bus.

Table 97. I2C State Register (I2CSTATE) - Description when DIAG = 0

BITS

FIELD

ACKV

ACK

10B

RSTR

SCLOUT

BUSY

RESET

R/W

RRR

ADDR

F55H

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