ZUSBOPTSC01ZAC datasheet(212/402 Pages) ZILOG

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I2C Master/Slave Controller

P R E L I M I N A R Y

PS024604-1005

Z8 Encore!® Motor Control Flash MCUs

Product Specification

190

I2CSTATE_H—I2C State

This field defines the current state of the I2C Controller. It is the most significant nibble of

the internal state machine. Table 99 defines the states for this field.

I2CSTATE_L—Least significant nibble of the I2C state machine. This field defines the

substates for the states defined by I2CSTATE_H. Table 100 defines the values for this

field.

Table 98. I2C State Register (I2CSTATE) - Description when DIAG = 1

BITS

FIELD

I2CSTATE_H

I2CSTATE_L

RESET

R/W

ADDR

F55H

Table 99. I2CSTATE_H

State

Encoding

State Name

State Description

0000

Idle

I2C bus is idle or I2C controller is disabled.

0001

Slave Start

I2C controller has received a START condition.

0010

Slave Bystander

Address did not match; ignore remainder of transaction.

0011

Slave Wait

Waiting for STOP or RESTART condition after sending a Not

Acknowledge instruction.

0100

Master Stop2

Master completing STOP condition (SCL = 1, SDA = 1).

0101

Master Start/Restart

MASTER mode sending START condition (SCL = 1, SDA = 0).

0110

Master Stop1

Master initiating STOP condition (SCL = 1, SDA = 0).

0111

Master Wait

Master received a Not Acknowledge instruction, waiting for

software to assert STOP or START control bits.

1000

Slave Transmit Data

9 substates, one for each data bit and one for the Acknowledge.

1001

Slave Receive Data

9 substates, one for each data bit and one for the Acknowledge.

1010

Slave Receive Addr1

Slave receiving first address byte (7- and 10-bit addressing)

9 substates, one for each address bit and one for the

Acknowledge.

1011

Slave Receive Addr2

Slave Receiving second address byte (10-bit addressing)

9 substates, one for each address bit and one for the

Acknowledge.

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