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ZUSBOPTSC01ZAC 数据表(PDF) 213 Page - Zilog, Inc. |
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ZUSBOPTSC01ZAC 数据表(HTML) 213 Page - Zilog, Inc. |
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213 / 402 page ![]() PS024604-1005 P R E L I M I N A R Y I2C State Register Z8FMC16100 Series Flash MCU Product Specification 191 1100 Master Transmit Data 9 substates, one for each data bit and one for the Acknowledge. 1101 Master Receive Data 9 substates, one for each data bit and one for the Acknowledge. 1110 Master Transmit Addr1 Master sending first address byte (7- and 10-bit addressing) 9 substates, one for each address bit and one for the Acknowledge. 1111 Master Transmit Addr2 Master sending second address byte (10-bit addressing) 9 substates, one for each address bit and one for the Acknowledge. Table 100. I2CSTATE_L State I2CSTATE_H Substate I2CSTATE_L Substate Name State Description 0000–0100 0000 — There are no substates for these I2CSTATE_H values. 0110–0111 0000 — There are no substates for these I2CSTATE_H values. 0101 0000 Master Start Initiating a new transaction 0001 Master Restart Master is ending one transaction and starting a new one without letting the bus go idle. 1000–1111 0111 send/receive bit 7 Sending/Receiving most significant bit 0110 send/receive bit 6 0101 send/receive bit 5 0100 send/receive bit 4 0011 send/receive bit 3 0010 send/receive bit 2 0001 send/receive bit 1 0000 send/receive bit 0 Sending/Receiving least significant bit 1000 send/receive Acknowledge Sending/Receiving Acknowledge Table 99. I2CSTATE_H (Continued) State Encoding State Name State Description |
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