ZUSBOPTSC01ZAC datasheet(209/402 Pages) ZILOG

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PS024604-1005

P R E L I M I N A R Y

I2C Baud Rate High and Low Byte Registers

Z8FMC16100 Series Flash MCU

Product Specification

187

STOP—Send Stop Condition

When set, this bit causes the I2C Controller (when configured as the Master) to send the

STOP condition after the byte in the I2C Shift register has completed transmission or after

a byte has been received in a receive operation. When set, this bit is reset by the I2C Con-

troller after a STOP condition has been sent or by deasserting the IEN bit. If this bit is 1, it

cannot be cleared to 0 by writing to the register.

If STOP is set while a slave mode transaction is underway, the STOP bit will be cleared by

hardware.

BIRQ—Baud Rate Generator Interrupt Request

This bit is ignored when the I2C Controller is enabled. If this bit is set = 1 when the I2C

Controller is disabled (IEN = 0) the baud rate generator is used as an additional timer caus-

ing an interrupt to occur every time the baud rate generator counts down to one. The baud

rate generator runs continuously in this mode, generating periodic interrupts.

TXI—Enable TDRE interrupts

This bit enables interrupts when the I2C Data register is empty.

NAK—Send NAK

Setting this bit sends a Not Acknowledge condition after the next byte of data has been

received. It is automatically deasserted after the Not Acknowledge is sent or the IEN bit is

cleared. If this bit is 1, it cannot be cleared to 0 by writing to the register.

FLUSH—Flush Data

Setting this bit clears the I2C Data register and sets the TDRE bit to 1. This bit allows flush-

ing of the I2C Data register when an NAK condition is received after the next data byte

has been written to the I2C Data register. Reading this bit always returns 0.

FILTEN—I2C Signal Filter Enable

Setting this bit enables low-pass digital filters on the SDA and SCL input signals. This

function provides the spike suppression filter required in I2C Fast Mode. These filters

reject any input pulse with periods less than a full system clock cycle. The filters introduce

a 3-system clock cycle latency on the inputs.

I2C Baud Rate High and Low Byte Registers

The I2C Baud Rate High and Low Byte registers, shown in Tables 95 and 96, combine to

form a 16-bit reload value, BRG[15:0], for the I2C Baud Rate Generator. The I2C baud rate

is calculated using the following equation.

If BRG = 0000h, use 10000h in the equation):

I2C Baud Rate (bits/s) =

System Clock Frequency (Hz)

4 x BRG[15:0]

Note:

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