ZUSBOPTSC01ZAC datasheet(205/402 Pages) ZILOG

205 / 402 page

PS024604-1005

P R E L I M I N A R Y

Slave Transactions

Z8FMC16100 Series Flash MCU

Product Specification

183

d. Set IEN = 1, NAK = 0 in the I2C Control Register.

2. The master initiates a transfer, sending the first address byte. The SLAVE mode I2C

controller recognizes the start of a 10-bit address with a match to SLA[9:8] and

detects the R/W bit = 0 (a Write from the master to the slave). The I2C controller

acknowledges, indicating it is available to accept the transaction.

3. The master sends the second address byte. The SLAVE mode I2C controller compares

the second address byte with the value in SLA[7:0]. If there is a match, the SAM bit in

the I2CISTAT Register is set = 1, causing a slave address match interrupt. The RD bit

is set = 0, indicating a write to the slave. If a match occurs, the I2C controller acknowl-

edges on the I2C bus, indicating it is available to accept the data.

4. The software responds to the slave address match interrupt by reading the I2CISTAT

required.

5. The master sees the Acknowledge and sends a RESTART instruction, followed by the

first address byte with the R/W set to 1. The SLAVE mode I2C controller recognizes

the RESTART instruction followed by the first address byte with a match to

SLA[9:8]

, and detects the R/W = 1 (the master reads from the slave). The slave I2C

controller sets the SAM bit in the I2CISTAT Register, which causes the slave address

match interrupt. The RD bit is set = 1. The SLAVE mode I2C controller acknowledges

on the bus.

6. The software responds to the interrupt by reading the I2CISTAT Register, clearing the

SAM

bit. The software loads the initial data byte into the I2CDATA Register and sets

the TXI bit in the I2CCTL Register.

7. The master starts the data transfer by asserting SCL Low. After the I2C controller has

data available to transmit, the SCL is released, and the master proceeds to shift the

first data byte.

8. After the first bit of the first data byte has been transferred, the I2C controller sets the

TDRE

bit which asserts the transmit data interrupt.

9. The software responds to the transmit data interrupt by loading the next data byte into

the I2CDATA Register.

10. The I2C master shifts in the remainder of the data byte. The master transmits the

Acknowledge (or Not Acknowledge, if this byte is the final data byte).

11. The bus cycles through steps 7 to 10 until the final byte has been transferred. If the

software has not yet loaded the next data byte when the master brings SCL Low to

transfer the most significant data bit, the slave I2C controller holds SCL Low until the

data register is written.

When a Not Acknowledge is received by the slave, the I2C controller sets the NCKI bit

in the I2CISTAT Register, causing the NAK interrupt to be generated.

ZUSBOPTSC01ZAC 数据表(PDF) 205 Page - Zilog, Inc.

ZUSBOPTSC01ZAC 数据表(HTML) 205 Page - Zilog, Inc.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载