ZUSBOPTSC01ZAC datasheet(208/402 Pages) ZILOG

208 / 402 page

I2C Master/Slave Controller

P R E L I M I N A R Y

PS024604-1005

Z8 Encore!® Motor Control Flash MCUs

Product Specification

186

SPRS—Stop/Restart Condition Interrupt

This bit is set when the I2C Controller is enabled in Slave mode and detects a STOP or

RESTART condition during a transaction directed to this slave. This bit clears when the

I2CISTAT register is read. Read the RSTR bit of the I2CSTATE register to determine

whether the interrupt was caused by a STOP or RESTART condition.

NCKI—NAK Interrupt

In Master mode, this bit is set when a Not Acknowledge condition is received or sent and

neither the START nor the STOP bit is active. In Master mode, this bit can only be cleared

by setting the START or STOP bits.

In Slave mode, this bit is set when a Not Acknowledge condition is received (Master read-

ing data from Slave), indicating the Master is finished reading. A STOP or RESTART con-

dition follows. In Slave mode this bit clears when the I2CISTAT register is read.

I2C Control Register

The I2C Control Register, shown in Table 94, enables and configures I2C operation.

NOTE: R/W1 - bit may be set (write 1) but not cleared.

IEN—I2C Enable

This bit enables the I2C Controller.

START—Send Start Condition

When set, this bit causes the I2C Controller (when configured as the Master) to send the

Start condition. Once asserted, it is cleared by the I2C Controller after it sends the Start

condition or by deasserting the IEN bit. If this bit is 1, it cannot be cleared by writing to

the bit. After this bit is set, the START condition is sent if there is data in the I2CDATA or

I2CSHIFT register. If there is no data in one of these registers, the I2C Controller waits

until data is loaded. If this bit is set while the I2C Controller is shifting out data, it gener-

ates a RESTART condition after the byte shifts and the acknowledge phase completes. If

the STOP bit is also set, it also waits until the STOP condition is sent before the START

condition.

If START is set while a slave mode transaction is underway to this device, the START bit

will be cleared and ARBLST bit in the Interrupt Status register will be set.

Table 94. I2C Control Register (I2CCTL)

BITS

FIELD

IEN

START

STOP

BIRQ

TXI

NAK

FLUSH

FILTEN

RESET

R/W

R/W1

R/W

R/W1

R/W

ADDR

F52H

ZUSBOPTSC01ZAC 数据表(PDF) 208 Page - Zilog, Inc.

ZUSBOPTSC01ZAC 数据表(HTML) 208 Page - Zilog, Inc.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载