ZUSBOPTSC01ZAC datasheet(201/402 Pages) ZILOG

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PS024604-1005

P R E L I M I N A R Y

Slave Transactions

Z8FMC16100 Series Flash MCU

Product Specification

179

1. The software configures the controller for operation as a slave in 7-bit addressing

mode, as follows.

a. Initialize the MODE field in the I2C Mode Register for either SLAVE ONLY mode

or MASTER/SLAVE mode with 7-bit addressing.

b. Optionally set the GCE bit.

c. Initialize the SLA[6:0] bits in the I2C Slave Address Register.

d. Set IEN = 1 in the I2C Control Register. Set NAK = 0 in the I2C Control Register.

2. The bus master initiates a transfer, sending the address byte. In SLAVE mode, the I2C

controller recognizes its own address and detects that the R/W bit = 0 (written from

the master to the slave). The I2C controller acknowledges, indicating it is available to

accept the transaction. The SAM bit in the I2CISTAT Register is set to 1, causing an

interrupt. The RD bit in the I2CISTAT Register is cleared to 0, indicating a Write to the

slave. The I2C controller holds the SCL signal Low, waiting for the software to load

the first data byte.

3. The software responds to the interrupt by reading the I2CISTAT Register (which

clears the SAM bit). After seeing the SAM bit to 1, the software checks the RD bit.

Because RD = 0, no immediate action is required until the first byte of data is received.

If software is only able to accept a single byte it sets the NAK bit in the I2CCTL Regis-

ter at this time.

4. The master detects the Acknowledge and sends the byte of data.

5. The I2C controller receives the data byte and responds with Acknowledge or Not

Acknowledge depending on the state of the NAK bit in the I2CCTL Register. The I2C

controller generates the receive data interrupt by setting the RDRF bit in the I2CISTAT

6. The software responds by reading the I2CISTAT Register, finding the RDRF bit = 1

and reading the I2CDATA Register clearing the RDRF bit. If software can accept only

one more data byte it sets the NAK bit in the I2CCTL Register.

7. The master and slave loops through steps 4 to 6 until the master detects a Not

Acknowledge instruction or runs out of data to send.

8. The master sends the STOP or RESTART signal on the bus. Either of these signals can

cause the I2C controller to assert a STOP interrupt (the STOP bit = 1 in the I2CISTAT

action in response to the STOP interrupt other than reading the I2CISTAT Register to

clear the STOP bit in the I2CISTAT Register.

Slave Address

W=0

Data

A/A

P/S

Figure 32. Data Transfer Format—Slave Receive Transaction with 7-Bit Address

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