ZUSBOPTSC01ZAC datasheet(199/402 Pages) ZILOG

199 / 402 page

PS024604-1005

P R E L I M I N A R Y

Slave Transactions

Z8FMC16100 Series Flash MCU

Product Specification

177

17. The I2C controller loads the I2C Shift Register with the contents of the I2C Data Reg-

ister (the third address transfer).

18. The I2C controller sends 11110b, followed by the two most-significant bits of the

slave read address and a 1 (Read).

19. The I2C slave sends an Acknowledge by pulling the SDA signal Low during the next

High period of SCL.

20. The I2C controller shifts in a byte of data from the slave.

21. The I2C controller asserts the Receive interrupt.

22. The software responds by reading the I2C Data Register. If the next data byte is to be

the final byte, the software must set the NAK bit of the I2C Control Register.

23. The I2C controller sends an Acknowledge or Not Acknowledge to the I2C slave, based

on the value of the NAK bit.

24. If there are more bytes to transfer, the I2C controller returns to Step 18.

25. The I2C controller generates a NAK interrupt (the NCKI bit in the I2CISTAT Regis-

ter).

26. The software responds by setting the STOP bit of the I2C Control Register.

27. A STOP condition is sent to the I2C slave.

Slave Transactions

The following sections describe Read and Write transactions to the I2C controller config-

ured for 7- and 10-bit slave modes.

Slave Address Recognition

The following slave address recognition options are supported.

Slave 7-Bit Address Recognition Mode.

If IRM = 0 during the address phase and the

controller is configured for MASTER/SLAVE or SLAVE 7-bit address mode, the hard-

ware detects a match to the 7-bit slave address defined in the I2CSLVAD Register and

generates the slave address match interrupt (the SAM bit = 1 in the I2CISTAT Register).

The I2C controller automatically responds during the Acknowledge phase with the value

in the NAK bit of the I2CCTL Register.

Slave 10-Bit Address Recognition Mode.

If IRM = 0 during the address phase and the

controller is configured for MASTER/SLAVE or SLAVE 10-bit address mode, the hard-

ware detects a match to the 10-bit slave address defined in the I2CMODE and I2CSLVAD

registers and generates the slave address match interrupt (the SAM bit = 1 in the I2CISTAT

the value in the NAK bit of the I2CCTL Register.

ZUSBOPTSC01ZAC 数据表(PDF) 199 Page - Zilog, Inc.

ZUSBOPTSC01ZAC 数据表(HTML) 199 Page - Zilog, Inc.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载