ZUSBOPTSC01ZAC datasheet(189/402 Pages) ZILOG

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PS024604-1005

P R E L I M I N A R Y

I2C Interrupts

Z8FMC16100 Series Flash MCU

Product Specification

167

I2C Interrupts

The I2C controller contains multiple interrupt sources that are combined into one interrupt

request signal to the interrupt controller. If the I2C controller is enabled, the source of the

interrupt is determined by which bits are set in the I2CISTAT Register. If the I2C control-

ler is disabled, the BRG controller can be used to generate general-purpose timer inter-

rupts.

Each interrupt source, other than the baud rate generator interrupt, features an associated

bit in the I2CISTAT Register that clears automatically when software reads the register or

performs another task, such as reading/writing the data register.

Transmit Interrupts

Transmit interrupts (TDRE bit = 1 in I2CISTAT) occur under the following conditions, both

of which must be true.

• The transmit data register is empty and the TXI bit = 1 in the I2C Control Register

• The I2C controller is enabled, with one of the following:

–

The first bit of a 10-bit address is shifted out

–

The first bit of the final byte of an address is shifted out and the RD bit is deas-

serted

–

The first bit of a data byte is shifted out

Writing to the I2C Data Register always clears the TRDE bit to 0.

Receive Interrupts

Receive interrupts (RDRF bit = 1 in I2CISTAT) occur when a byte of data has been

received by the I2C controller. The RDRF bit is cleared by reading from the I2C Data Reg-

ister. If the RDRF interrupt is not serviced prior to the completion of the next Receive

byte, the I2C controller holds SCL Low during the final data bit of the next byte until

RDRF

is cleared, to prevent receive overruns. A receive interrupt does not occur when a

slave receives an address byte or for data bytes following a slave address that did not

match. An exception is if the Interactive Receive Mode (IRM) bit is set in the I2CMODE

SLAVE mode.

Slave Address Match Interrupts

Slave address match interrupts (SAM bit = 1 in I2CISTAT) occur when the I2C controller is

in SLAVE mode and an address is received that matches the unique slave address. The

General Call Address (0000_0000) and STARTBYTE (0000_0001) are recognized if the

GCE

bit = 1 in the I2CMODE Register. The software checks the RD bit in the I2CISTAT

Address and STARTBYTE address are also distinguished by the RD bit. The General Call

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