ZUSBOPTSC01ZAC datasheet(182/402 Pages) ZILOG

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Serial Peripheral Interface

P R E L I M I N A R Y

PS024604-1005

Z8 Encore!® Motor Control Flash MCUs

Product Specification

160

TXST—Transmit Status

0 = No data transmission currently in progress.

1 = Data transmission currently in progress.

SLAS—Slave Select

If SPI enabled as a Slave,

0 = SS input pin is asserted (Low)

1 = SS input is not asserted (High).

If SPI enabled as a Master, this bit is not applicable.

SPI Mode Register

The SPI Mode Register configures the character bit width and the direction and value of

the SS pin.

Reserved—Must be 0.

DIAG - Diagnostic Mode Control bit

This bit is for SPI diagnostics. Setting this bit allows the Baud Rate Generator value to be

read using the SPIBRH and SPIBRL register locations.

0 = Reading SPIBRH, SPIBRL returns the value in the SPIBRH and SPIBRL registers

1 = Reading SPIBRH returns bits [15:8] of the SPI Baud Rate Generator; and reading SPI-

BRL returns bits [7:0] of the SPI Baud Rate Counter. The Baud Rate Counter High and

Low byte values are not buffered.

Exercise caution if reading the values while the BRG is counting.

NUMBITS[2:0]—Number of Data Bits Per Character to Transfer

This field contains the number of bits to shift for each character transfer. Refer to the SPI

Data Register description for information on valid bit positions when the character length

is less than 8-bits.

Table 87. SPI Mode Register (SPIMODE)

BITS

FIELD

Reserved

DIAG

NUMBITS[2:0]

SSIO

SSV

RESET

00H

R/W

RR/W

ADDR

F63H

Caution:

ZUSBOPTSC01ZAC 数据表(PDF) 182 Page - Zilog, Inc.

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