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ZUSBOPTSC01ZAC 数据表(PDF) 366 Page - Zilog, Inc. |
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ZUSBOPTSC01ZAC 数据表(HTML) 366 Page - Zilog, Inc. |
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366 / 402 page ![]() PS024604-1005 P R E L I M I N A R Y Appendix A—Register Tables Z8 Encore!® Motor Control Flash MCUs Product Specification 344 Hex Address: F72 Hex Address: F73 ADC Raw Data High Byte Register (ADCRD_H) BITS 7 6 5 4 3 2 1 0 FIELD ADCRDH RESET X R/W R ADDR F71H Bit Position Value (H) Description [7:0] 00H–FFH ADC Raw Data High Byte The data in this register is the raw data coming from the SAR Block. It will change as the conversion is in progress. This register is used for testing only. ADC Data Low Bits Register (ADCD_L) BITS 7 6 5 4 3 2 1 0 FIELD ADCDL Reserved RESET XX R/W RR ADDR F73H Bit Position Value (H) Description [7:6] 00–11b ADC Low Bits These bits are the 2 least significant bits of the 10-bit ADC output. These bits are undefined after a Reset. The low bits are latched into this register whenever the ADC Data High Byte register is read. [5:0] Reserved 0 Reserved—Must Be 0. |
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