ZUSBOPTSC01ZAC datasheet(370/402 Pages) ZILOG

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PS024604-1005

P R E L I M I N A R Y

Appendix A—Register Tables

Z8 Encore!® Motor Control Flash MCUs

Product Specification

348

Hex Address: F87

Trim Control

Hex Addresses: F88–F8F

Reserved

[2]

FLPEN

Flash Low Power Mode Enable

Flash Low Power Mode is disabled.

Flash Low Power Mode is enabled. The Flash will be powered down during idle

periods of the clock and powered up during Flash reads. This bit should only be

set if the frequency of the primary oscillator source is 8MHz or lower. The reset

value of this bit is controlled by the LPDEN option bit during reset.

[1:0]

SCKSEL

System Clock Oscillator Select

Internal precision oscillator functions as system clock at 5.6MHz

Reserved

Crystal oscillator or external clock driver functions as system clock

Watch-Dog Timer oscillator functions as system clock

Oscillator Divide Register (OSCDIV)

BITS

FIELD

DIV

RESET

00H*

R/W

ADDR

F87H

* The reset value is 08H if the option bit LPDEN is 0.

Bit

Position

Value

(H)

Description

[7:0]

DIV

00H to

FFH

Oscillator Divide

00H - divider is disabled, all other entries are the divide value for scaling the

system clock.

Bit

Position

Value

(H)

Description

ZUSBOPTSC01ZAC 数据表(PDF) 370 Page - Zilog, Inc.

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