TUSB7340 datasheet(18/122 Pages) TI2

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CL1

CL2

VSSOSC

Crystal

Figure 6-1. Oscillation Circuit

6.3.2.2 External Clock

When using an external clock source, the reference clock should have a ±100 PPM or better frequency stability

and have less than 50-ps absolute peak to peak jitter or less than 25-ps peak to peak jitter after applying the

USB 3.0 jitter transfer function. XI should be tied to the clock source and XO should be left floating. The input

clock must be 1.8-V LVCMOS; this input is not 3.3-V tolerant.

6.3.2.3 External Crystal

An external 2-MΩ feedback resistor is required between XI and XO when using a crystal. See Crystal

Specification for additional crystal specifications.

6.4 Programming

6.4.1 Two-Wire Serial-Bus Interface

The host controller provides a two-wire serial-bus interface to load subsystem identification information and

specific register defaults from an external EEPROM. The serial-bus interface signals include SDA and SCL. The

use of an external EEPROM is optional. The TUSB73x0 will function with the default settings. For motherboard

down applications, BIOS can be used to set all of the options available on the TUSB73x0.

On a PCIe Add-in Card, an EEPROM is only needed if any of the following is true:

• Mark one or more USB ports as non-removable.

• Disable one or more USB ports.

• Set a PCIe Subsystem ID and Subsystem Vendor ID.

• Change the default de-emphasis/swing/equalizer settings of the SuperSpeed USB ports.

• Change the default L0s and L1 latency values for PCIe.

• Change the default PWRON polarity to active high instead of active low.

6.4.1.1 Serial-Bus Interface Implementation

To enable the serial-bus interface, a pullup resistor must be implemented on the SCL signal. At the rising edge

of PERST# or GRST#, whichever occurs later in time, the SCL terminal is checked for a pullup resistor. If one

is detected, then bit 3 (SBDETECT) in Serial Bus Control and Status Register) is set. Software may disable the

serial-bus interface at any time by writing a 0b to the SBDETECT bit. If no external EEPROM is required, then

the serial-bus interface is permanently disabled by attaching a pull-down resistor to the SCL signal.

TUSB7320, TUSB7340

SLLSE76Q – MARCH 2011 – REVISED MARCH 2024

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