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TUSB7340 数据表(PDF) 68 Page - Texas Instruments |
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TUSB7340 数据表(HTML) 68 Page - Texas Instruments |
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68 / 122 page  Table 8-94. General Control 0 Register Description BIT FIELD NAME ACCESS DESCRIPTION 31:12 RSVD r Reserved. Returns zeros when read. 11:9 L1_EXIT_LAT_ASYNC(1) rw L1 Exit Latency for Asynchronous Clock. This value in this field is the value reported in the L1_LATENCY field in the Link Capabilities Register when the CCC bit in the Link Control Register is 0. This field defaults to 110b. 8:6 L1_EXIT_LAT_COMMON(1) rw L1 Exit Latency for Common Clock. This value in this field is the value reported in the L1_LATENCY field in the Link Capabilities Register when the CCC bit in the Link Control Register is 1. This field defaults to 110b. 5:3 L0s_EXIT_LAT_ASYNC(1) rw L0s Exit Latency for Asynchronous Clock. This value in this field is the value reported in the L0s_LATENCY field in the Link Capabilities Register when the CCC bit in the Link Control Register is 0. This field defaults to 011b. 2:0 L0s_EXIT_LAT_COMMON(1) rw L0s Exit Latency for Common Clock. This value in this field is the value reported in the L0s_LATENCY field in the Link Capabilities Register when the CCC bit in the Link Control Register is 1. This field defaults to 011b. (1) This bit is reset by a PCI Express reset (PERST), a GRST, or the internally generated power-on-reset. 8.1.62 General Control 1 Register This register is a read/write register is used to control various functions of the TUSB73X0. This register is reset by a PCI Express reset (PERST#), a GRST#, or the internally-generated power-on-reset. PCI register offset: D8h Register type: Read-Only, Read/Write Default value: 0000 001Bh Table 8-95. PCI Register D8h Bit No. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 Table 8-96. General Control 1 Register Description BIT FIELD NAME ACCESS DESCRIPTION 31:6 RSVD r Reserved. Returns zeros when read. 5:3 L1ASPM_ENTRY_TIMER(1) rw L1ASPM Entry Timer. This field specifies the value of the L1ASPM Entry Timer. This field defaults to 011, corresponding to a value of 8 µs. 2:0 L0s_ENTRY_TIMER(1) rw L0s Entry timer. This field specifies the value of the L0s Entry timer. This field defaults to 011, corresponding to a value of 4 µs. (1) This bit is reset by a PCI Express reset (PERST), a GRST, or the internally generated power-on-reset. TUSB7320, TUSB7340 SLLSE76Q – MARCH 2011 – REVISED MARCH 2024 www.ti.com 68 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: TUSB7320 TUSB7340 |
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