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TUSB7340 数据表(PDF) 71 Page - Texas Instruments |
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TUSB7340 数据表(HTML) 71 Page - Texas Instruments |
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71 / 122 page  Table 8-100. USB Control Register Description (continued) BIT FIELD NAME ACCESS DESCRIPTION 7 USB3_PORT4_NON_REM(1) rw USB 3.0 Port 4 Non-removable. When this bit is set to 1, the TUSB73X0 forces the DR bit to 1 in the Port Status and Control Register corresponding to USB 3.0 Port 4. For the TUSB7320 Port 4 is not present and this bit has no effect. 6 USB3_PORT3_NON_REM(1) rw USB 3.0 Port 3 Non-removable. When this bit is set to 1, the TUSB73X0 forces the DR bit to 1 in the Port Status and Control Register corresponding to USB 3.0 Port 3. For the TUSB7320 Port 3 is not present and this bit has no effect. 5 USB3_PORT2_NON_REM(1) rw USB 3.0 Port 2 Non-removable. When this bit is set to 1, the TUSB73X0 forces the DR bit to 1 in the Port Status and Control Register corresponding to USB 3.0 Port 2. 4 USB3_PORT1_NON_REM(1) rw USB 3.0 Port 1 Non-removable. When this bit is set to 1, the TUSB73X0 forces the DR bit to 1 in the Port Status and Control Register corresponding to USB 3.0 Port 1. 3 USB2_PORT4_NON_REM(1) rw USB 2.0 Port 4 Non-removable. When this bit is set to 1, the TUSB73X0 forces the DR bit to 1 in the Port Status and Control Register corresponding to USB 2.0 Port 4. For the TUSB7320 Port 4 is not present and this bit has no effect. 2 USB2_PORT3_NON_REM(1) rw USB 2.0 Port 3 Non-removable. When this bit is set to 1, the TUSB73X0 forces the DR bit to 1 in the Port Status and Control Register corresponding to USB 2.0 Port 3. For the TUSB7320 Port 3 is not present and this bit has no effect. 1 USB2_PORT2_NON_REM(1) rw USB 2.0 Port 2 Non-removable. When this bit is set to 1, the TUSB73X0 forces the DR bit to 1 in the Port Status and Control Register corresponding to USB 2.0 Port 2. 0 USB2_PORT1_NON_REM(1) rw USB 2.0 Port 1 Non-removable. When this bit is set to 1, the TUSB73X0 forces the DR bit to 1 in the Port Status and Control Register corresponding to USB 2.0 Port 1. (1) This bit is reset by a PCI Express reset (PERST), a GRST, or the internally generated power-on-reset. (2) This bit is a sticky bit and is reset by a global reset (GRST) or the internally-generated power-on-reset. 8.1.65 De-Emphasis and Swing Control Register This register is used to control the de-emphasis and transmit swing settings for each of the USB 3.0 ports when the default setting is overridden through the Custom PHY Transmit/Receive Control Register. This register is reset by a PCI Express reset (PERST#), a GRST#, or the internally-generated power-on-reset. PCI register offset: E4h Register type: Read/Write Default value: 0000 0000h Table 8-101. PCI Register E4h Bit No. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 www.ti.com TUSB7320, TUSB7340 SLLSE76Q – MARCH 2011 – REVISED MARCH 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 71 Product Folder Links: TUSB7320 TUSB7340 |
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