TUSB7340 datasheet(21/122 Pages) TI2

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Figure 6-7 illustrates the serial interface protocol during a multibyte serial EEPROM download. The serial-bus

protocol starts exactly the same as a 1-byte read. The only difference is that multiple data bytes are transferred.

The number of transferred data bytes is controlled by the host controller. After each data byte, the host controller

issues acknowledge (logic low) if more data bytes are requested. The transfer ends after a host controller no

acknowledge (logic high) followed by a stop condition.

Figure 6-7. Serial-Bus Protocol – Multibyte Read

Bit 7 (PROT_SEL) in the serial-bus control and status register changes the serial-bus protocol. Each of the

three previous serial-bus protocol figures illustrates the PROT_SEL bit default (logic low). When this control

bit is asserted, the word address and corresponding acknowledge are removed from the serial-bus protocol.

This feature allows the system designer a second serial-bus protocol option when selecting external EEPROM

devices.

6.4.1.3 Serial-Bus EEPROM Application

A serial EEPROM interface is implemented to pre-load several registers. The registers and corresponding bits

that are loaded through the EEPROM are provided in Table 6-4.

Table 6-4. EEPROM Register Loading Map

SERIAL EEPROM WORD ADDRESS

BYTE DESCRIPTION

00h

TUSB73X0 Function Indicator (00h)

01h

Number of Bytes (19h)

02h

PCI D0h, Subsystem Vendor ID, Byte 0

03h

PCI D1h, Subsystem Vendor ID, Byte 1

04h

PCI D2h, Subsystem ID, Byte 0

05h

PCI D3h, Subsystem ID, Byte 1

06h

PCI D4h, General Control 0, Byte 0

07h

PCI D5h, General Control 0, Byte 1

08h

PCI D8h, General Control 1, Byte 0

09h

PCI DCh, General Control 2, Byte 0

0Ah

PCI E0h, USB Control, Byte 0

0Bh

PCI E1h, USB Control, Byte 1

0Ch

PCI E2h, USB Control, Byte 2

0Dh

PCI E3h, USB Control, Byte 3

0Eh

PCI E4h, De-emphasis and Swing Control, Byte 0

0Fh

PCI E5h, De-emphasis and Swing Control, Byte 1

10h

PCI E6h, De-emphasis and Swing Control, Byte 2

11h

PCI E7h, De-emphasis and Swing Control, Byte 3

12h

PCI E8h, Equalizer Control, Byte 0

13h

PCI E9h, Equalizer Control, Byte 1

14h

PCI EAh, Equalizer Control, Byte 2

15h

PCI EBh, Equalizer Control, Byte 3

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TUSB7320, TUSB7340

SLLSE76Q – MARCH 2011 – REVISED MARCH 2024

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