TUSB7340 datasheet(57/122 Pages) TI2

57 / 122 page

Table 8-60. Link Capabilities Register Description (continued)

BIT

FIELD NAME

ACCESS

DESCRIPTION

17:15

L1_LATENCY

L1 Exit Latency. This field indicates the time that it takes to transition

from the L1 state to the L0 state. The value reported by this

field is determined by either the L1_EXIT_LAT_ASYNC field or the

L1_EXIT_LAT_COMMON field in the General Control Register 0.

14:12

L0S_LATENCY

L0s Exit Latency. This field indicates the time that it takes to transition

from the L0s state to the L0 state. The value reported by this

field is determined by either the L0s_EXIT_LAT_ASYNC field or the

L0s_EXIT_LAT_COMMON field in the General Control Register 0.

11:10

ASLPMS

Active State Link PM Support. This field indicates the level of active

state power management that the TUSB73X0 supports. The value

11b indicates support for both L0s and L1 through active state power

management.

9:4

MLW

Maximum Link Width. This field is encoded 000001b to indicate that the

TUSB73X0 only supports a 1x PCI Express link.

3:0

MLS

Maximum Link Speed. This field is encoded 0010b to indicate that the

TUSB73X0 supports link speeds of 5 Gb/s and 2.5 Gb/s.

8.1.43 Link Control Register

The Link Control Register indicates is used to control link specific behavior.

PCI register offset: 80h

Default value: 0000h

Table 8-61. PCI Register 80h

Bit

No.

Reset

State

Table 8-62. Link Control Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

15:9

RSVD

Reserved. Returns zeros when read.

EN_CPM

Enable Clock Power Management.

Extended Synch.

CCC

Common Clock Configuration. This bit is set when a common clock is

provided to both ends of the PCI Express link. This bit is also used to

select the L0s exit latency and L1 exit latency.

0 – Reference clock is asynchronous (L0s exit latency and

L1 exit latency based on the L0s_EXIT_LAT_ASYNC and

L1_EXIT_LAT_ASYNC fields in the General Control Register 0)

1 – Reference clock is synchronous (L0s exit latency and L1 exit latency

based on the L0s_EXIT_LAT_COMMON and L1_EXIT_LAT_COMMON

fields in the General Control Register 0)

Retrain Link. This bit has no function and is read only zero.

Link Disable. This bit has no function and is read only zero.

RCB

Read Completion Boundary.

RSVD

Reserved. Returns zero when read.

1:0

ASLPMC

Active State Link PM Control. This field is used to enable and disable

active state PM.

00 – Active State PM Disabled

01 – L0s Entry Enabled

10 – L1 Entry Enabled

11 – L0s and L1 Entry Enable

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TUSB7320, TUSB7340

SLLSE76Q – MARCH 2011 – REVISED MARCH 2024

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