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TUSB7340 数据表(PDF) 67 Page - Texas Instruments

部件名 TUSB7340
功能描述  TUSB73x0 USB 3.0 xHCI Host Controller
PDF  122 Pages
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制造商  TI2 [Texas Instruments]
网页  https://www.ti.com
标志 TI2 - Texas Instruments

TUSB7340 数据表(HTML) 67 Page - Texas Instruments

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8.1.60 Subsystem Access Register
This register is a read/write register and the contents of this register are aliased to the Subsystem Vendor ID and
Subsystem ID Registers at PCI Offsets 2Ch and 2Eh. This register is reset by a PCI Express reset (PERST#), a
GRST#, or the internally-generated power-on-reset.
PCI register offset: D0h
Register type: Read/Write
Default value: 0000 0000h
Table 8-91. PCI Register D0h
Bit
No.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reset
State
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
No.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
State
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 8-92. Subsystem Access Register Description
BIT
FIELD NAME
ACCESS
DESCRIPTION
31:16
SubsystemID(1)
rw
Subsystem ID. The value written to this field is aliased to the Subsystem
ID Register at PCI Offset 2Eh.
15:0
SubsystemVendorID(1)
rw
Subsystem Vendor ID. The value written to this field is aliased to the
Subsystem Vendor ID Register at PCI Offset 2Ch.
(1)
This bit is reset by a PCI Express reset (PERST), a GRST, or the internally generated power-on-reset.
8.1.61 General Control 0 Register
This register is a read/write register is used to control various functions of the TUSB73X0. This register is reset
by a PCI Express reset (PERST#), a GRST#, or the internally-generated power-on-reset.
PCI register offset: D4h
Register type: Read/Write
Default value: 0000 0D9Bh
Table 8-93. PCI Register D4h
Bit
No.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reset
State
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
No.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
State
0
0
0
0
1
1
0
1
1
0
0
1
1
0
1
1
www.ti.com
TUSB7320, TUSB7340
SLLSE76Q – MARCH 2011 – REVISED MARCH 2024
Copyright © 2024 Texas Instruments Incorporated
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Product Folder Links: TUSB7320 TUSB7340



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