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TUSB7340 数据表(PDF) 59 Page - Texas Instruments |
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TUSB7340 数据表(HTML) 59 Page - Texas Instruments |
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59 / 122 page  Table 8-66. Device Capabilities 2 Register Description BIT FIELD NAME ACCESS DESCRIPTION 31:5 RSVD r Reserved. Returns zeros when read. 4 CPLT_TO_DIS_SUP r Completion Timeout Disable Supported. This bit is read only 1b indicating that the completion timeout disable mechanism is supported. 3:0 CPLT_TO_RANGES r Completion Timeout Ranges Supported. This field is read only 0000b indicating that completion timeout programming is not supported. 8.1.46 Device Control 2 Register The Device Control 2 Register controls PCI Express device specific parameters. PCI register offset: 98h Register type: Read-only, Read/Write Default value: 0800h Table 8-67. PCI Register 98h Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 Table 8-68. Device Control 2 Register Description BIT FIELD NAME ACCESS DESCRIPTION 15:5 RSVD r Reserved. Returns zeros when read. 4 CPTL_TO_DIS rw Completion Timeout Disable. 3:0 CPLT_TO_VALUE r Completion Timeout Value. This field is read only 0000b indicating that completion timeout programming is not supported. 8.1.47 Link Control 2 Register The Link Control 2 Register indicates is used to control link specific behavior. PCI register offset: A0h Register type: Read-only, Read/Write Default value: 0000h Table 8-69. PCI Register A0h Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 Table 8-70. Link Control 2 Register Description BIT FIELD NAME ACCESS DESCRIPTION 15:13 RSVD r Reserved. Returns zeros when read. 12 COMPLIANCE_DEEMPH(1) rw Compliance De-Emphasis. This bit is sticky and is only reset by a Global Reset. 11 COMPLIANCE_SOS(1) rw Compliance SOS. This bit is sticky and is only reset by a Global Reset. 10 ENT_MOD_COMPLIANCE (1) rw Enter Modified Compliance. This bit is sticky and is only reset by a Global Reset. 9:7 TRANSMIT_MARGIN(1) rw Transmit Margin. This bit is sticky and is only reset by a Global Reset. 6 SEL_DEEMPH r Selectable De-Emphasis. This bit has no function and is read only zero. 5 HW_AUTO_SPEED_DIS r Hardware Autonomous Speed Disable. This bit is read only zero because this function is not supported. www.ti.com TUSB7320, TUSB7340 SLLSE76Q – MARCH 2011 – REVISED MARCH 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 59 Product Folder Links: TUSB7320 TUSB7340 |
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