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TUSB7340 数据表(PDF) 81 Page - Texas Instruments

部件名 TUSB7340
功能描述  TUSB73x0 USB 3.0 xHCI Host Controller
PDF  122 Pages
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制造商  TI2 [Texas Instruments]
网页  https://www.ti.com
标志 TI2 - Texas Instruments

TUSB7340 数据表(HTML) 81 Page - Texas Instruments

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8.2.8 Correctable Error Mask Register
The Correctable Error Status Register reports the status of individual errors as they occur. Software may clear
these bits only by writing a 1 to the desired location.
PCI Express Extended Register Offset: 114h
Register type: Read-Only, Read/Write
Default value: 0000 2000h
Table 8-118. PCI Express Extended Register 114h
Bit
No.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reset
State
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
No.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
State
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 8-119. Bit Descriptions – Correctable Error Mask Register
BIT
FIELD NAME
ACCESS
DESCRIPTION
31:14
RSVD
r
Reserved. Returns zeros when read.
13
ANFEM(1)
rw
Advisory Non-Fatal Error Mask.
0 – Error Condition is Unmasked
1 – Error Condition is Masked
12
REPLAY_TMOUT_MASK(1)
rw
Replay Timer Timeout Mask.
0 – Error Condition is Unmasked
1 – Error Condition is Masked
11:9
RSVD
r
Reserved. Returns zeros when read.
8
REPLAY_ROLL_MASK(1)
rw
REPLAY_NUM Rollover Mask.
0 – Error Condition is Unmasked
1 – Error Condition is Masked
7
BAD_DLLP_MASK(1)
rw
Bad DLLP Error Mask.
0 – Error Condition is Unmasked
1 – Error Condition is Masked
6
BAD_TLP_MASK(1)
rw
Bad TLP Error Mask.
0 – Error Condition is Unmasked
1 – Error Condition is Masked
5:1
RSVD
r
Reserved. Returns zeros when read.
0
RX_ERROR_MASK(1)
rw
Receiver Error Mask.
0 – Error Condition is Unmasked
1 – Error Condition is Masked
(1)
This bit is reset by a PCI Express reset (PERST), a GRST, or the internally generated power-on-reset.
www.ti.com
TUSB7320, TUSB7340
SLLSE76Q – MARCH 2011 – REVISED MARCH 2024
Copyright © 2024 Texas Instruments Incorporated
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Product Folder Links: TUSB7320 TUSB7340



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