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TUSB7340 数据表(PDF) 48 Page - Texas Instruments

部件名 TUSB7340
功能描述  TUSB73x0 USB 3.0 xHCI Host Controller
PDF  122 Pages
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制造商  TI2 [Texas Instruments]
网页  https://www.ti.com
标志 TI2 - Texas Instruments

TUSB7340 数据表(HTML) 48 Page - Texas Instruments

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Table 8-34. Power Management Control/Status Register Description (continued)
BIT
FIELD NAME
ACCESS
DESCRIPTION
3
NO_SOFT_RESET
r
No Soft Reset. This bit returns 1 indicating that no internal reset
is generated and the device retains its configuration context when
transitioning from the D3hot state to the D0 state.
2
RSVD
r
Reserved. Returns zero when read.
1:0
PWR_STATE
rw
Power State. This 2-bit field is used both to determine the current
power state of the function and to set the function into a new power
state. This field is encoded as follows:00 = D001 = D110 = D211 =
D3hot.
8.1.26 Power Management Bridge Support Extension Register
This read-only register is not applicable to the TUSB73X0 and returns 00h when read.
PCI register offset: 46h
Register type: Read-only
Default value: 00h
Table 8-35. PCI Register 46h
Bit No.
7
6
5
4
3
2
1
0
Reset State
0
0
0
0
0
0
0
0
8.1.27 Power Management Data Register
This read-only register is not applicable to the TUSB73X0 and returns 00h when read.
PCI register offset: 47h
Register type: Read-only
Default value: 00h
Table 8-36. PCI Register 47h
Bit No.
7
6
5
4
3
2
1
0
Reset State
0
0
0
0
0
0
0
0
8.1.28 MSI Capability ID Register
This read-only register identifies the linked list item as the register for Message Signaled Interrupts Capabilities.
The register returns 05h when read.
PCI register offset: 48h
Register type: Read-only
Default value: 05h
Table 8-37. PCI Register 48h
Bit No.
7
6
5
4
3
2
1
0
Reset State
0
0
0
0
0
1
0
1
TUSB7320, TUSB7340
SLLSE76Q – MARCH 2011 – REVISED MARCH 2024
www.ti.com
48
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Copyright © 2024 Texas Instruments Incorporated
Product Folder Links: TUSB7320 TUSB7340



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