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TUSB7340 数据表(PDF) 79 Page - Texas Instruments |
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TUSB7340 数据表(HTML) 79 Page - Texas Instruments |
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79 / 122 page  Table 8-115. Bit Descriptions – Uncorrectable Error Severity Register (continued) BIT FIELD NAME ACCESS DESCRIPTION 14 CPL_TIMEOUT_SEVR(1) rw Completion Timeout Severity. 0 – Error Condition is signaled using ERR_NONFATAL 1 – Error Condition is signaled using ERR_FATAL 13 FC_ERROR_SEVR(1) rw Flow Control Error Severity. 0 – Error Condition is signaled using ERR_NONFATAL1 – Error Condition is signaled using ERR_FATAL 12 PSN_TLP_SEVR(1) rw Poisoned TLP Severity. 0 – Error Condition is signaled using ERR_NONFATAL 1 – Error Condition is signaled using ERR_FATAL 11:6 RSVD r Reserved. Returns zeros when read. 5 RSVD r Reserved. Returns 1 when read. 4 DLL_ERROR_SEVR(1) rw Data Link Protocol Error Severity. 0 – Error Condition is signaled using ERR_NONFATAL 1 – Error Condition is signaled using ERR_FATAL 3:0 RSVD r Reserved. Returns zeros when read. (1) This bit is reset by a PCI Express reset (PERST), a GRST, or the internally generated power-on-reset. 8.2.7 Correctable Error Severity Register The Correctable Error Status Register reports the status of individual errors as they occur. Software may clear these bits only by writing a 1 to the desired location. PCI Express Extended Register Offset: 110h Register type: Read-Only, Read/Clear Default value: 0000 0000h Table 8-116. PCI Express Extended Register 110h Bit No. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 8-117. Bit Descriptions – Correctable Error Severity Register BIT FIELD NAME ACCESS DESCRIPTION 31:14 RSVD r Reserved. Returns zeros when read. 13 ANFES(1) rcu Advisory Non-Fatal Error Status. This bit is asserted when an Advisory Non-Fatal Error has been reported. 12 REPLAY_TMOUT(1) rcu Replay Timer Timeout. This bit is asserted when the replay timer expires for a pending request or completion that has not been acknowledged. 11:9 RSVD r Reserved. Returns zeros when read. 8 REPLAY_ROLL(1) rcu REPLAY_NUM Rollover. This bit is asserted when the replay counter rolls over when a pending request or completion has not been acknowledged. 7 BAD_DLLP(1) rcu Bad DLLP Error. This bit is asserted when an 8b/10b error was detected by the PHY during the reception of a DLLP. 6 BAD_TLP(1) rcu Bad TLP Error. This bit is asserted when an 8b/10b error was detected by the PHY during the reception of a TLP. 5:1 RSVD r Reserved. Returns zeros when read. www.ti.com TUSB7320, TUSB7340 SLLSE76Q – MARCH 2011 – REVISED MARCH 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 79 Product Folder Links: TUSB7320 TUSB7340 |
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