TUSB7340 datasheet(52/122 Pages) TI2

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8.1.34 Serial Bus Release Number Register (SBRN)

This read only register is set to 30h to indicate that the TUSB73X0 is compliant to release 3.0 of the Universal

Serial Bus Specification.

PCI register offset: 60h

Default value: 00h

Table 8-46. PCI Register 60h

Bit No.

Reset State

8.1.35 Frame Length Adjustment Register (FLADJ)

This register is used to adjust any offset from the clock source that generates the clock that drives the SOF

counter. When a new value is written to this register, the length of the frame is adjusted for all USB buses

implemented by the TUSB73X0. This register is only reset by a Global Reset.

PCI register offset: 61h

Default value: 20h

Table 8-47. PCI Register 61h

Bit No.

Reset State

Table 8-48. Frame Length Adjustment Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

7:6

RSVD

Reserved. Return zeros when read.

5:0

FRAME_LENGTH(1)

Frame Length Timing Value. Each decimal value change to this register

corresponds to 16 high-speed bit times. The SOF cycle time is equal to

59488 plus the value in this field. The default value is decimal 32 (20h),

which gives a SOF cycle time of 60000.

(1)

This bit is a sticky bit and is reset by a global reset (GRST) or the internally-generated power-on-reset.

8.1.36 PCI Express Capability ID Register

This read-only register identifies the linked list item as the register for PCI Express Capabilities. The register

returns 10h when read.

PCI register offset: 70h

Default value: 10h

Table 8-49. PCI Register 70h

Bit No.

Reset State

TUSB7320, TUSB7340

SLLSE76Q – MARCH 2011 – REVISED MARCH 2024

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