TUSB7340 datasheet(39/122 Pages) TI2

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8.1.5 Status Register

The status register provides information about the PCI Express interface to the system.

PCI register offset: 06h

Default value: 0010h

Table 8-6. PCI Register 06h

Bit

No.

Reset

State

Table 8-7. Status Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

PAR_ERR

rcu

Detected parity error. This bit is set when the PCI Express interface receives a

poisoned TLP. This bit is set regardless of the state of bit 6 (PERR_ENB) in the

command register (offset 04h, see Command Register).

0 = No parity error detected

1 = Parity error detected

SYS_ERR

rcu

Signaled system error. This bit is set when the host controller sends an

ERR_FATAL or ERR_NONFATAL message and bit 8 (SERR_ENB) in the

command register (offset 04h, see Command Register) is set.

0 = No error signaled

1 = ERR_FATAL or ERR_NONFATAL signaled

MABORT

rcu

Received controller abort. This bit is set when the PCI Express interface of the

host controller receives a completion-with-unsupported-request status.

0 = Unsupported request not received on the PCI Express interface

1 = Unsupported request received on the PCI Express interface

TABORT_REC

rcu

Received target abort. This bit is set when the PCI Express interface of the

host controller receives a completion-with-completer-abort status.

0 = Completer abort not received on the PCI Express interface

1 = Completer abort received on the PCI Express interface

TABORT_SIG

rcu

Signaled target abort. This bit is set when the PCI Express interface completes

a request with completer abort status.

0 = Completer abort not signaled on the PCI Express interface

1 = Completer abort signaled on the PCI Express interface

10:9

DEVSEL_TIMING

DEVSEL Timing. These bits are read only zero, because they do not apply to

PCI Express.

DATAPAR

rcu

controller data parity error. This bit is set if bit 6 (PERR_ENB) in the command

receives a completion with data marked as poisoned on the PCI Express

interface or poisons a write request received on the PCI Express interface.

0 = No uncorrectable data error detected on the primary interface

1 = Uncorrectable data error detected on the primary interface.

FBB_CAP

Fast back-to-back capable. This bit does not have a meaningful context for a

PCI Express device and is hardwired to 0b.

RSVD

Reserved. Returns zeros when read.

66MHZ

66 MHz capable. This bit does not have a meaningful context for a PCI

Express device and is hardwired to 0b.

CAPLIST

Capabilities list. This bit returns 1b when read, indicating that the host

controller supports additional PCI capabilities.

INT_STATUS

Interrupt Status. This bit reflects the interrupt status of the function.

2:0

RSVD

Reserved. Returns zeros when read.

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TUSB7320, TUSB7340

SLLSE76Q – MARCH 2011 – REVISED MARCH 2024

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