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TUSB7340 数据表(PDF) 54 Page - Texas Instruments |
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TUSB7340 数据表(HTML) 54 Page - Texas Instruments |
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54 / 122 page  8.1.39 Device Capabilities Register The Device Capabilities Register indicates the device specific capabilities of the TUSB73X0. PCI register offset: 74h Register type: Read-only, Hardware Update Default value: 0000 8FC3h Table 8-53. PCI Register 74h Bit No. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 1 0 0 0 1 1 1 1 1 1 0 0 0 0 1 1 Table 8-54. Device Capabilities Register Description BIT FIELD NAME ACCESS DESCRIPTION 31:29 RSVD r Reserved. Return zeros when read. 28 FLR r Function Level Reset. This bit is set to 0 because the TUSB73X0 has only one function. 27:26 CSPLS ru Captured Slot Power Limit Scale. The value in this register is programmed by the host by issuing a Set_Slot_Power_Limit Message. When a Set_Slot_Power_Limit Message is received bits 9:8 are written to this field. The value in this register specifies the scale used for the Slot Power Limit. 00 – 1.0x 01 – 0.1x 10 – 0.01x 11 – 0.001x 25:18 CSPLV ru Captured Slot power Limit Value. The value in this register is programmed by the host by issuing a Set_Slot_Power_Limit Message. When a Set_Slot_Power_Limit Message is received bits 7:0 are written to this field. The value in this register in combination with the Slot power Limit Scale value, specifies the upper limit of power supplied to the slot. The power limit is calculated by multiplying the value in this field by the value in the Slot Power Limit Scale field. 17:16 RSVD r Reserved. Return zeros when read. 15 RBER r Role Based Error Reporting. This bit is hardwired to 1 indicating that the TUSB73X0 supports Role Based Error Reporting 14:12 RSVD r Reserved. Return zeros when read. 11:9 EP_L1_LAT r Endpoint L1 Acceptable Latency. This field indicates the acceptable latency for a transition from L1 to L0 State. This field can be programmed by writing to the L1_LATENCY field in the General Control Register 2. The default value for this register is the latency for the PHY to exit the L1 state. This field cannot be programmed to be less than the latency for the PHY to exit the L1 state. 8:6 EP_L0S_LAT r Endpoint L0s Acceptable Latency. This field indicates the acceptable latency for a transition from L0s to L0 State. This field can be programmed by writing to the L0s_LATENCY field in the General Control Register 2. The default value for this register is the latency for the PHY to exit the L0s state. This field cannot be programmed to be less than the latency for the PHY to exit the L0s state. 5 ETFS r Extended Tag Field Supported. This field indicates the size of the tag field and is encoded as 0. TUSB7320, TUSB7340 SLLSE76Q – MARCH 2011 – REVISED MARCH 2024 www.ti.com 54 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: TUSB7320 TUSB7340 |
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