TUSB7340 datasheet(73/122 Pages) TI2

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Table 8-104. Equalizer Control Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

31:28

PORT4_EQ_INIT(1)

Port 4 Equalizer - Initialization Mode. When the PORT4_EQ_OV bit is

set to 1, these bits are used as the source for the Equalizer init values

for port 4 of the PHY. For details on the behavior of the equalizer values

refer to Table 6-3. For the TUSB7320 Port 4 is not present and these bits

have no effect.

27:24

PORT4_EQ_FUNC(1)

Port 4 Equalizer- Functional Mode. When the PORT4_EQ_OV bit is set

to 1, these bits are used as the source for the Equalizer func values for

port 4 of the PHY. For details on the behavior of the equalizer values

refer to Table 6-3. For the TUSB7320 Port 4 is not present and these bits

have no effect.

23:20

PORT3_EQ_INIT(1)

Port 3 Equalizer - Initialization Mode. When the PORT3_EQ_OV bit is

set to 1, these bits are used as the source for the Equalizer init values

for port 3 of the PHY. For details on the behavior of the equalizer values

refer to Table 6-3. For the TUSB7320 Port 3 is not present and these bits

have no effect.

19:16

PORT3_EQ_FUNC(1)

Port 3 Equalizer- Functional Mode. When the PORT3_EQ_OV bit is set

to 1, these bits are used as the source for the Equalizer func values for

port 3 of the PHY. For details on the behavior of the equalizer values

refer to Table 6-3. For the TUSB7320 Port 3 is not present and these bits

have no effect.

15:12

PORT2_EQ_INIT(1)

Port 2 Equalizer - Initialization Mode. When the PORT2_EQ_OV bit is

set to 1, these bits are used as the source for the Equalizer init values

for port 3 of the PHY. For details on the behavior of the equalizer values

refer to Table 6-3.

11:8

PORT2_EQ_FUNC(1)

Port 2 Equalizer- Functional Mode. When the PORT2_EQ_OV bit is set

to 1, these bits are used as the source for the Equalizer func values for

port 3 of the PHY. For details on the behavior of the equalizer values

refer to Table 6-3.

7:4

PORT1_EQ_INIT(1)

Port 1 Equalizer - Initialization Mode. When the PORT1_EQ_OV bit is

set to 1, these bits are used as the source for Equalizer init values for

port 1 of the PHY. For details on the behavior of the equalizer values

refer toTable 6-3

3:0

PORT1_EQ_FUNC(1)

Port 1 Equalizer- Functional Mode. When the PORT1_EQ_OV bit is set

to 1, these bits are used as the source for Equalizer func values for port

1 of the PHY. For details on the behavior of the equalizer values refer to

Table 6-3.

(1)

This bit is reset by a PCI Express reset (PERST), a GRST, or the internally generated power-on-reset.

8.1.67 Custom PHY Transmit/Receive Control Register

This register is used to enable the override of the default de-emphasis, transmit swing, and receiver equalization

settings for each of the USB 3.0 ports. This register is reset by a PCI Express reset (PERST#), a GRST#, or the

internally-generated power-on-reset.

PCI register offset: ECh

Default value: 0000 0000h

Table 8-105. PCI Register ECh

Bit

No.

Reset

State

Bit

No.

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TUSB7320, TUSB7340

SLLSE76Q – MARCH 2011 – REVISED MARCH 2024

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