TUSB7340 datasheet(38/122 Pages) TI2

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8.1.4 Command Register

The Command register provides control over the TUSB73X0 interface to the PCIe interface

PCI register offset: 04h

Default value: 0000h

Table 8-4. PCI Register 04h

Bit

No.

Reset

State

Table 8-5. Bit Command Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

15:11

RSVD

Reserved. Returns zeros when read.

INT_DISABLE

INTx# Disable. This bit enables device specific interrupts.

FBB_ENB

Fast back-to-back enable. The host controller does not generate fast back-to-

back transactions; therefore, this bit returns 0 when read.

SERR_ENB

SERR enable bit. When this bit is set, the host controller can signal fatal and

nonfatal errors on the PCI Express interface on behalf of SERR assertions

detected on the PCI bus.

0 = Disable the reporting of nonfatal errors and fatal errors (default)

1 = Enable the reporting of nonfatal errors and fatal errors

STEP_ENB

Address/data stepping control. The host controller does not support address/

data stepping, and this bit is hardwired to 0b.

PERR_ENB

Controls the setting of bit 8 (DATAPAR) in the status register (offset 06h, see

Status Register) in response to a received poisoned TLP from PCI Express.

A received poisoned TLP is forwarded with bad parity to conventional PCI

regardless of the setting of this bit.

0 = Disables the setting of the controller data parity error bit (default)

1 = Enables the setting of the controller data parity error bit

VGA_ENB

VGA palette snoop enable. The host controller does not support VGA palette

snooping; therefore, this bit returns 0b when read.

MWI_ENB

Memory write and invalidate enable. The host controller does not support

memory write and invalidate enable; therefore, this bit returns 0b when read.

SPECIAL

Special cycle enable. This host controller does not respond to special cycle

transactions; therefore, this bit returns 0 when read.

CONTROLLER_ENB

Bus controller enable. When this bit is set, the host controller is enabled to

initiate transactions on the PCI Express interface.

0 = PCI Express interface cannot initiate transactions. The host controller must

disable the response to memory and I/O transactions on the PCI interface

(default).

1 = PCI Express interface can initiate transactions. The host controller can

forward memory and I/O transactions from PCI secondary interface to the PCI

Express interface.

MEMORY_ENB

Memory space enable. Setting this bit enables the host controller to respond to

memory transactions on the PCI Express interface.

0 = PCI Express receiver cannot process downstream memory transactions and

must respond with an unsupported request (default)

1 = PCI Express receiver can process downstream memory transactions. The

host controller can forward memory transactions to the PCI interface.

IO_ENB

I/O space enable. Setting this bit enables the host controller to respond to I/O

transactions on the PCI Express interface.

0 = PCI Express receiver cannot process downstream I/O transactions and

must respond with an unsupported request (default)

1 = PCI Express receiver can process downstream I/O transactions. The host

controller can forward I/O transactions to the PCI interface.

TUSB7320, TUSB7340

SLLSE76Q – MARCH 2011 – REVISED MARCH 2024

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