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TUSB7340 数据表(PDF) 58 Page - Texas Instruments

部件名 TUSB7340
功能描述  TUSB73x0 USB 3.0 xHCI Host Controller
PDF  122 Pages
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制造商  TI2 [Texas Instruments]
网页  https://www.ti.com
标志 TI2 - Texas Instruments

TUSB7340 数据表(HTML) 58 Page - Texas Instruments

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8.1.44 Link Status Register
The Link Status Register indicates current state of the PCI Express Link.
PCI register offset: 82h
Register type: Read-only
Default value: 101xh
Table 8-63. PCI Register 82h
Bit
No.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
State
0
0
0
1
0
0
0
0
0
0
0
1
0
0
x
x
Table 8-64. Link Status Register Description
BIT
FIELD NAME
ACCESS
DESCRIPTION
15
LINK_ABS
r
Link Autonomous Bandwidth Status. This bit has no function and is read
only zero.
14
LINK_BMS
r
Link Bandwidth Management Status. This bit has no function and is read
only zero.
13
DLL_ACTIVE
r
Data Link Layer Active. This bit has no function and is read only zero.
12
SCC
r
Slot Clock Configuration. This bit is 1, because the TUSB73X0 uses the
100-MHz differential reference clock provided by the platform.
11
LT
r
Link Training. This bit has no function and is read only zero.
10
TE
r
Retrain Link. This bit has no function and is read only zero.
9:4
NLW
r
Negotiated Link Width. This field is read only 000001b indicating the lane
width is 1x.
3:0
LS
r
Link Speed. This field indicates the negotiated link speed.
8.1.45 Device Capabilities 2 Register
The Device Capabilities 2 Register indicates the device specific capabilities of the TUSB73X0.
PCI register offset: 94h
Register type: Read-only
Default value: 0000 0010h
Table 8-65. PCI Register 94h
Bit
No.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reset
State
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
No.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
State
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
TUSB7320, TUSB7340
SLLSE76Q – MARCH 2011 – REVISED MARCH 2024
www.ti.com
58
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Copyright © 2024 Texas Instruments Incorporated
Product Folder Links: TUSB7320 TUSB7340



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