TUSB7340 datasheet(53/122 Pages) TI2

53 / 122 page

8.1.37 Next Item Pointer Register

The contents of this read-only register indicate the next item in the linked list of capabilities for the TUSB73X0.

This register reads C0h pointing to the MSI-X Capability registers.

PCI register offset: 71h

Default value: C0h

Table 8-50. PCI Register 71h

Bit No.

Reset State

8.1.38 PCI Express Capabilities Register

This register indicates the capabilities of the TUSB73X0 related to PCI Express.

PCI register offset: 72h

Default value: 0002h

Table 8-51. PCI Register 72h

Bit

No.

Reset

State

Table 8-52. PCI Express Capabilities Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

15:14

RSVD

Reserved. Returns zeros when read.

13:9

INT_NUM

Interrupt Message Number. This field is used for MSI and MSI-X support.

SLOT

Slot Implemented. This bit is not valid for the TUSB73X0 and is read

only zero.

7:4

DEV_TYPE

Device/Port Type. This read only field returns 0000b indicating that the

device is a PCI Express Endpoint.

3:0

VERSION

Capability Version. This field returns 0010b indicating revision two of the

PCI Express capability.

www.ti.com

TUSB7320, TUSB7340

SLLSE76Q – MARCH 2011 – REVISED MARCH 2024

Submit Document Feedback

Product Folder Links: TUSB7320 TUSB7340

TUSB7340 数据表(PDF) 53 Page - Texas Instruments

TUSB7340 数据表(HTML) 53 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载