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TUSB7340 数据表(PDF) 76 Page - Texas Instruments |
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TUSB7340 数据表(HTML) 76 Page - Texas Instruments |
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76 / 122 page  8.2.3 Next Capability Offset / Capability Version Register This read-only register identifies the next location in the PCI Express Extended Capabilities link list. The upper 12 bits in this register shall be 150h, indicating that the Device Serial Number Capability starts at offset 150h. The least significant four bits identify the revision of the current capability block as 2h. PCI Express Extended Register Offset: 100h Register type: Read-Only Default value: 1502h Table 8-109. PCI Express Extended Register 102h Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 0 0 0 1 0 1 0 1 0 0 0 0 0 0 1 0 8.2.4 Uncorrectable Error Status Register The Uncorrectable Error Status Register reports the status of individual errors as they occur. Software may clear these bits only by writing a 1 to the desired location. PCI Express Extended Register Offset: 104h Register type: Read-Only, Read/Clear Default value: 0000 0000h Table 8-110. PCI Express Extended Register 104h Bit No. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit No. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 8-111. Custom PHY Transmit/Receive Control Register Description BIT FIELD NAME ACCESS DESCRIPTION 31:21 RSVD r Reserved. Returns zeros when read. 20 UR_ERROR(1) rcu Unsupported Request Error. This bit is asserted when an Unsupported Request is received. 19 ECRC_ERROR(1) rcu Extended CRC Error. This bit is asserted when an Extended CRC error is detected. 18 MAL_TLP(1) rcu Malformed TLP. This bit is asserted when a malformed TLP is detected. 17 RX_OVERFLOW(1) rcu Receiver Overflow. This bit is asserted when the flow control logic detects that the transmitting device has illegally exceeded the number of credits that were issued. 16 UNXP_CPL(1) rcu Unexpected Completion. This bit is asserted when a completion packet is received that does not correspond to an issued request. 15 CPL_ABORT(1) rcu Completer Abort. This bit is asserted when the TUSB73X0 signals a Completer Abort. 14 CPL_TIMEOUT(1) rcu Completion Timeout. This bit is asserted when no completion has been received for an issued request before the timeout period. 13 FC_ERROR(1) rcu Flow Control Error. This bit is asserted when a flow control protocol error is detected either during initialization or during normal operation. 12 PSN_TLP(1) rcu Poisoned TLP. This bit is asserted when a poisoned TLP is received. TUSB7320, TUSB7340 SLLSE76Q – MARCH 2011 – REVISED MARCH 2024 www.ti.com 76 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: TUSB7320 TUSB7340 |
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