TUSB7340 datasheet(47/122 Pages) TI2

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8.1.24 Power Management Capabilities Register

The read-only register indicates the capabilities of the TUSB73X0 related to PCI power management.

PCI register offset: 42h

Default value: xxx3h

Table 8-31. PCI Register 42h

Bit

No.

Reset

State

Table 8-32. Power Management Capabilities Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

15:11

PME_SUPPORT

PME# support. This five-bit field indicates the power states from which the

TUSB73X0 may assert PME#. If the AUX_DET pin is 1, this field is 11111. If

the AUX_DET pin is 0, this field is 01111.

D2_SUPPORT

This bit returns a 1 when read, indicating that the function supports the D2

device power state.

D1_SUPPORT

This bit returns a 1 when read, indicating that the function supports the D1

device power state.

8:6

AUX_CURRENT

3.3 Vaux auxiliary current requirements. If the AUX_DET pin is 1, this field is

010. If the AUX_DET pin is 0, this field is 000.

DSI

Device Specific Initialization. This bit returns 0 when read, indicating that the

TUSB73X0 does not require special initialization beyond the standard PCI

configuration header before a generic class driver is able to use it.

RSVD

Reserved. Returns zero when read.

PME_CLK

PME# Clock.

2:0

PM_VERSION

Power Mgmt Version. This field returns 3’b011 indicating Rev 1.2

compatibility.

8.1.25 Power Management Control/Status Register

This register determines and changes the current power state of the TUSB73X0.

PCI register offset: 44h

Default value: 0008h

Table 8-33. PCI Register 44h

Bit

No.

Reset

State

Table 8-34. Power Management Control/Status Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

PME_STAT

PME# Status. This bit is sticky and is only reset by a Global Reset.

14:13

DATA_SCALE

Data Scale. This 2-bit field returns 0’s when read because the

TUSB73X0 does not use the Data Register.

12:9

DATA_SEL

Data Select. This 4-bit field returns 0’s when read because the

TUSB73X0 does not use the Data Register.

PME_EN

PME# Enable. This bit is sticky and is only reset by a Global Reset.

7:4

RSVD

Reserved. Returns zero when read.

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TUSB7320, TUSB7340

SLLSE76Q – MARCH 2011 – REVISED MARCH 2024

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