PSD834210MIT datasheet(62/89 Pages) STMICROELECTRONICS

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PSD834F2V

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is in Read mode (primary and secondary Flash

memory contents can be read). TSTAT is Low

when Flash memory Program or Erase cycles are

in progress, and also when data is being written to

the secondary Flash memory.

TSTAT and TERR can be configured as open-

drain type signals during an “ISC_ENABLE” com-

mand. This facilitates a wired-OR connection of

TSTAT signals from multiple PSD devices and a

wired-OR connection of TERR signals from those

same devices. This is useful when several PSD

devices are “chained” together in a JTAG environ-

ment.

Security and Flash memory Protection

When the security bit is set, the device cannot be

read on a Device Programmer or through the

JTAG Port. When using the JTAG Port, only a Full

Chip Erase command is allowed.

All other Program, Erase and Verify commands

are blocked. Full Chip Erase returns the part to a

non-secured blank state. The Security Bit can be

set in PSDsoft Express Configuration.

All primary and secondary Flash memory sectors

can individually be sector protected against era-

sures. The sector protect bits can be set in PSD-

soft Express Configuration.

INITIAL DELIVERY STATE

When delivered from ST, the PSD device has all

bits in the memory and PLDs set to 1. The PSD

Configuration Register bits are set to 0. The code,

configuration, and PLD logic are loaded using the

programming procedure. Information for program-

ming the device is available directly from ST.

Please contact your local sales representative.

Table 34. JTAG Enable Register

Note: 1. The state of Reset (Reset) does not interrupt (or prevent) JTAG operations if the JTAG signals are dedicated by an NVM Configu-

ration bit (via PSDsoft Express). However, Reset (Reset) prevents or interrupts JTAG operations if the JTAG enable register is used

to enable the JTAG signals.

Bit 0

JTAG_Enable

0 = off JTAG port is disabled.

1 = on JTAG port is enabled.

Bit 1