数据搜索系统，热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

预览 PDF HTML

PSD834210MIT 数据表(PDF) 70 Page - STMicroelectronics

部件名 PSD834210MIT
功能描述  Flash PSD, 3.3V Supply, for 8-bit MCUs 2 Mbit 256 Kbit Dual Flash Memories and 64 Kbit SRAM
PDF  89 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

PSD834210MIT 数据表(HTML) 70 Page - STMicroelectronics

Back Button PSD834210MIT Datasheet HTML 66Page - STMicroelectronics PSD834210MIT Datasheet HTML 67Page - STMicroelectronics PSD834210MIT Datasheet HTML 68Page - STMicroelectronics PSD834210MIT Datasheet HTML 69Page - STMicroelectronics PSD834210MIT Datasheet HTML 70Page - STMicroelectronics PSD834210MIT Datasheet HTML 71Page - STMicroelectronics PSD834210MIT Datasheet HTML 72Page - STMicroelectronics PSD834210MIT Datasheet HTML 73Page - STMicroelectronics PSD834210MIT Datasheet HTML 74Page - STMicroelectronics Next Button
Zoom Inzoom in Zoom Outzoom out
 70 / 89 page
background image
PSD834F2V
70/89
Table 43. CPLD Combinatorial Timing
Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD0. Decrement times by given amount.
Table 44. CPLD Macrocell Synchronous Clock Mode Timing
Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD0. Decrement times by given amount.
2. CLKIN (PD1) tCLCL = tCH + tCL .
Symbol
Parameter
Conditions
-10
-15
-20
PT
Aloc
Turbo
Off
Slew
rate1
Unit
Min
Max
Min
Max
Min
Max
tPD
CPLD Input Pin/
Feedback to CPLD
Combinatorial Output
40
45
50
+ 4
+ 20
– 6
ns
tEA
CPLD Input to CPLD
Output Enable
43
45
50
+ 20
– 6
ns
tER
CPLD Input to CPLD
Output Disable
43
45
50
+ 20
– 6
ns
tARP
CPLD Register Clear
or
Preset Delay
40
43
48
+ 20
– 6
ns
tARPW
CPLD Register Clear
or
Preset Pulse Width
25
30
35
+ 20
ns
tARD
CPLD Array Delay
Any
macrocell
25
29
33
+ 4
ns
Symbol
Parameter
Conditions
-10
-15
-20
PT
Aloc
Turbo
Off
Slew
rate1
Unit
Min
Max
Min
Max
Min
Max
fMAX
Maximum
Frequency
External Feedback
1/(tS+tCO)
22.2
18.8
15.8
MHz
Maximum
Frequency
Internal Feedback
(fCNT)
1/(tS+tCO–10)
28.5
23.2
18.8
MHz
Maximum
Frequency
Pipelined Data
1/(tCH+tCL)
40.0
33.3
31.2
MHz
tS
Input Setup Time
20
25
30
+ 4
+ 20
ns
tH
Input Hold Time
0
0
0
ns
tCH
Clock High Time
Clock Input
15
15
16
ns
tCL
Clock Low Time
Clock Input
10
15
16
ns
tCO
Clock to Output
Delay
Clock Input
25
28
33
– 6
ns
tARD
CPLD Array Delay
Any macrocell
25
29
33
+ 4
ns
tMIN
Minimum Clock
Period2
tCH+tCL
25
29
32
ns



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com