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PSD834210MIT 数据表(PDF) 68 Page - STMicroelectronics |
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PSD834210MIT 数据表(HTML) 68 Page - STMicroelectronics |
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68 / 89 page  PSD834F2V 68/89 Table 41. AC Symbols for PLD Timing Example: tAVLX – Time from Address Valid to ALE Invalid. Figure 35. Switching Waveforms – Key Signal Letters Signal Behavior A Address Input t Time C CEout Output L Logic Level Low or ALE D Input Data H Logic Level High E E Input V Valid G Internal WDOG_ON signal X No Longer a Valid Logic Level I Interrupt Input Z Float L ALE Input PW Pulse Width N Reset Input or Output P Port Signal Output Q Output Data RWR, UDS, LDS, DS, IORD, PSEN Inputs S Chip Select Input TR/W Input W Internal PDN Signal B VSTBY Output M Output Macrocell WAVEFORMS INPUTS OUTPUTS STEADY INPUT MAY CHANGE FROM HI TO LO MAY CHANGE FROM LO TO HI DON'T CARE OUTPUTS ONLY STEADY OUTPUT WILL BE CHANGING FROM HI TO LO WILL BE CHANGING LO TO HI CHANGING, STATE UNKNOWN CENTER LINE IS TRI-STATE AI03102 |
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