PSD834210MIT datasheet(12/89 Pages) STMICROELECTRONICS

12 / 89 page

PSD834F2V

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PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

I/O

These pins make up Port A. These port pins are configurable and can have the following

functions:

1. MCU I/O – write to or read from a standard output or input port.

2. CPLD macrocell (McellAB0-7) outputs.

3. Inputs to the PLDs.

4. Latched address outputs (see Table 5).

5. Address inputs. For example, PA0-3 could be used for A0-A3 when using an 80C51XA

in burst mode.

6. As the data bus inputs D0-D7 for non-multiplexed address/data bus MCUs.

7. D0/A16-D3/A19 in M37702M2 mode.

8. Peripheral I/O mode.

Note: PA0-PA3 can only output CMOS signals with an option for high slew rate. However,

PA4-PA7 can be configured as CMOS or Open Drain Outputs.

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

I/O

These pins make up Port B. These port pins are configurable and can have the following

functions:

1. MCU I/O – write to or read from a standard output or input port.

2. CPLD macrocell (McellAB0-7 or McellBC0-7) outputs.

3. Inputs to the PLDs.

4. Latched address outputs (see Table 5).

Note: PB0-PB3 can only output CMOS signals with an option for high slew rate. However,

PB4-PB7 can be configured as CMOS or Open Drain Outputs.

PC0

I/O

PC0 pin of Port C. This port pin can be configured to have the following functions:

1. MCU I/O – write to or read from a standard output or input port.

2. CPLD macrocell (McellBC0) output.

3. Input to the PLDs.

4. TMS Input2 for the JTAG Serial Interface.

This pin can be configured as a CMOS or Open Drain output.

PC1

I/O

PC1 pin of Port C. This port pin can be configured to have the following functions:

1. MCU I/O – write to or read from a standard output or input port.

2. CPLD macrocell (McellBC1) output.

3. Input to the PLDs.

4. TCK Input2 for the JTAG Serial Interface.

This pin can be configured as a CMOS or Open Drain output.

PC2

I/O

PC2 pin of Port C. This port pin can be configured to have the following functions:

1. MCU I/O – write to or read from a standard output or input port.

2. CPLD macrocell (McellBC2) output.

3. Input to the PLDs.

4. VSTBY – SRAM stand-by voltage input for SRAM battery backup.

This pin can be configured as a CMOS or Open Drain output.

PC3

I/O

PC3 pin of Port C. This port pin can be configured to have the following functions:

1. MCU I/O – write to or read from a standard output or input port.

2. CPLD macrocell (McellBC3) output.

3. Input to the PLDs.

4. TSTAT output2 for the JTAG Serial Interface.

5. Ready/Busy output for parallel In-System Programming (ISP).

This pin can be configured as a CMOS or Open Drain output.

PC4

I/O

PC4 pin of Port C. This port pin can be configured to have the following functions:

1. MCU I/O – write to or read from a standard output or input port.

2. CPLD macrocell (McellBC4) output.

3. Input to the PLDs.

4. TERR output2 for the JTAG Serial Interface.

5. Battery-on Indicator (VBATON). Goes High when power is being drawn from the

external battery.

This pin can be configured as a CMOS or Open Drain output.

Pin Name

Type

Description

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PSD834210MIT 数据表(PDF) 12 Page - STMicroelectronics

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