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PSD834210MIT 数据表(PDF) 43 Page - STMicroelectronics |
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PSD834210MIT 数据表(HTML) 43 Page - STMicroelectronics |
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43 / 89 page ![]() 43/89 PSD834F2V Figure 21. Interfacing the PSD with the 80C51X, 8-bit Data Bus 68HC11. Figure 22 shows a bus interface to a 68HC11 where the PSD is configured in 8-bit mul- tiplexed mode with E and R/W settings. The DPLD can be used to generate the READ and WR sig- nals for external devices. ADIO0 ADIO1 ADIO2 ADIO3 AD104 AD105 ADIO6 ADIO7 ADIO8 ADIO9 ADIO10 ADIO11 AD1012 AD1013 ADIO14 ADIO15 CNTL0 (WR) CNTL1(RD) CNTL 2 (PSEN) PD0-ALE PD1 PD2 RESET 31 33 36 2 3 4 5 43 42 41 40 39 38 37 24 25 26 27 28 29 30 A4D0 A5D1 A6D2 A7D3 A8D4 A9D5 A10D6 A11D7 A12 A13 A14 A18 A19 A17 A15 A16 A0 A1 A2 A3 A4D0 A5D1 A6D2 A7D3 A8D4 A9D5 A10D6 A11D7 A12 A16 A17 A18 A19 A15 A13 A14 TXD1 T2EX T2 T0 RST EA/WAIT BUSW A1 A0/WRH A2 A3 A4D0 A5D1 A6D2 A7D3 A8D4 A9D5 A10D6 A11D7 A12D8 A13D9 A14D10 A15D11 A16D12 A17D13 A18D14 A19D15 PSEN RD WRL PC0 PC1 PC3 PC4 PC5 PC6 PC7 ALE PSEN RD WR ALE 32 19 18 30 31 32 33 34 35 36 37 39 40 41 42 43 44 45 46 48 8 9 10 49 50 47 7 9 8 16 XTAL1 XTAL2 RXD0 TXD0 RXD1 21 20 11 13 6 29 28 27 25 24 23 22 21 20 19 18 17 14 13 12 11 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 7 6 5 4 3 2 52 51 A0 A1 A2 A3 80C51XA PSD RESET RESET 35 17 INT0 INT1 14 10 15 PC2 AI02883C |
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