PSD834210MIT datasheet(59/89 Pages) STMICROELECTRONICS

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PSD834F2V

Table 31. APD Counter Operation

SRAM Standby Mode (Battery Backup). The

PSD supports a battery backup mode in which the

contents of the SRAM are retained in the event of

a power loss. The SRAM has Voltage Stand-by

(VSTBY, PC2) that can be connected to an exter-

nal battery. When VCC becomes lower than VSTBY

then the PSD automatically connects to Voltage

Stand-by (VSTBY, PC2) as a power source to the

SRAM. The SRAM Standby Current (ISTBY) is typ-

ically 0.5 µA. The SRAM data retention voltage is

2 V minimum. The Battery-on Indicator (VBATON)

can be routed to PC4. This signal indicates when

the VCC has dropped below VSTBY.

PSD Chip Select Input (CSI, PD2)

PD2 of Port D can be configured in PSDsoft Ex-

press as PSD Chip Select Input (CSI). When Low,

the signal selects and enables the internal Flash

memory, EEPROM, SRAM, and I/O blocks for

Read or Write operations involving the PSD. A

High on PSD Chip Select Input (CSI, PD2) dis-

ables the Flash memory, EEPROM, and SRAM,

and reduces the PSD power consumption. How-

ever, the PLD and I/O signals remain operational

when PSD Chip Select Input (CSI, PD2) is High.

There may be a timing penalty when using PSD

Chip Select Input (CSI, PD2) depending on the

speed grade of the PSD that you are using. See

the timing parameter tSLQV in Table 50.

Input Clock

The PSD provides the option to turn off CLKIN

(PD1) to the PLD to save AC power consumption.

CLKIN (PD1) is an input to the PLD AND Array and

the Output Macrocells (OMC).

During Power-down mode, or, if CLKIN (PD1) is

not being used as part of the PLD logic equation,

the clock should be disabled to save AC power.

CLKIN (PD1) is disconnected from the PLD AND

Array or the Macrocells block by setting bits 4 or 5

to a 1 in PMMR0.

Input Control Signals

The PSD provides the option to turn off the input

control signals (CNTL0, CNTL1, CNTL2, Address

Strobe (ALE/AS, PD0) and DBE) to the PLD to

save AC power consumption. These control sig-

nals are inputs to the PLD AND Array. During

Power-down mode, or, if any of them are not being

used as part of the PLD logic equation, these con-

trol signals should be disabled to save AC power.

They are disconnected from the PLD AND Array

by setting bits 2, 3, 4, 5, and 6 to a 1 in PMMR2.

Figure 31. Reset (RESET) Timing

APD Enable Bit

ALE PD Polarity

ALE Level

APD Counter

Not Counting

Pulsing

Not Counting

Counting (Generates PDN after 15 Clocks)

tNLNH-PO

tOPR

AI02866b

RESET

tNLNH

tNLNH-A

tOPR

VCC

CC(min)

Power-On Reset

Warm Reset

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