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PSD834210MIT 数据表(PDF) 71 Page - STMicroelectronics |
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PSD834210MIT 数据表(HTML) 71 Page - STMicroelectronics |
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71 / 89 page ![]() 71/89 PSD834F2V Table 45. CPLD Macrocell Asynchronous Clock Mode Timing Symbol Parameter Conditions -10 -15 -20 PT Aloc Turbo Off Slew Rate Unit Min Max Min Max Min Max fMAXA Maximum Frequency External Feedback 1/(tSA+tCOA) 21.7 19.2 16.9 MHz Maximum Frequency Internal Feedback (fCNTA) 1/(tSA+tCOA–10) 27.8 23.8 20.4 MHz Maximum Frequency Pipelined Data 1/(tCHA+tCLA) 33.3 27 24.4 MHz tSA Input Setup Time 10 12 13 + 4 + 20 ns tHA Input Hold Time 12 15 17 ns tCHA Clock High Time 17 22 25 + 20 ns tCLA Clock Low Time 13 15 16 + 20 ns tCOA Clock to Output Delay 36 40 46 + 20 – 6 ns tARD CPLD Array Delay Any macrocell 25 29 33 + 4 ns tMINA Minimum Clock Period 1/fCNTA 36 42 49 ns |
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