PSD834210MIT datasheet(60/89 Pages) STMICROELECTRONICS

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PSD834F2V

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RESET TIMING AND DEVICE STATUS AT RESET

Upon Power-up, the PSD requires a Reset (RE-

SET) pulse of duration tNLNH-PO after VCC is

steady. During this period, the device loads inter-

nal configurations, clears some of the registers

and sets the Flash memory into Operating mode.

After the rising edge of Reset (RESET), the PSD

remains in the Reset mode for an additional peri-

od, tOPR, before the first memory access is al-

lowed.

The Flash memory is reset to the Read mode upon

Power-up.

Sector

Select

(FS0-FS7

and

CSBOOT0-CSBOOT3) must all be Low, Write

Strobe (WR, CNTL0) High, during Power On Re-

set for maximum security of the data contents and

to remove the possibility of a byte being written on

the first edge of Write Strobe (WR, CNTL0). Any

Flash memory Write cycle initiation is prevented

automatically when VCC is below VLKO.

Warm Reset

Once the device is up and running, the device can

be reset with a pulse of a much shorter duration,

tNLNH. The same tOPR period is needed before the

device is operational after warm reset. Figure 31

shows the timing of the Power-up and warm reset.

I/O Pin, Register and PLD Status at Reset

Table 32 shows the I/O pin, register and PLD sta-

tus during Power On Reset, warm reset and Pow-

er-down mode. PLD outputs are always valid

during warm reset, and they are valid in Power On

Reset once the internal PSD Configuration bits are

loaded. This loading of PSD is completed typically

long before the VCC ramps up to operating level.

Once the PLD is active, the state of the outputs are

determined by the PSDabel equations.

Reset of Flash Memory Erase and Program

Cycles

A Reset (RESET) also resets the internal Flash

memory state machine. During a Flash memory

Program or Erase cycle, Reset (RESET) termi-

nates the cycle and returns the Flash memory to

the Read mode within a period of tNLNH-A.

Table 32. Status During Power-On Reset, Warm Reset and Power-down Mode

Note: 1. The SR_cod and PeriphMode bits in the VM Register are always cleared to 0 on Power-On Reset or Warm Reset.

Port Configuration

Power-On Reset

Warm Reset

Power-down Mode

MCU I/O

Input mode

Unchanged

PLD Output

Valid after internal PSD

configuration bits are

loaded

Valid

Depends on inputs to PLD

(addresses are blocked in

PD mode)

Address Out

Tri-stated

Not defined

Data Port

Tri-stated

Peripheral I/O

Tri-stated

Power-On Reset

Warm Reset

Power-down Mode

PMMR0 and PMMR2

Cleared to 0

Unchanged

Macrocells flip-flop status

Cleared to 0 by internal

Power-On Reset

Depends on .re and .pr

equations

Depends on .re and .pr

equations

VM Register1

Initialized, based on the

selection in PSDsoft

Configuration menu

Initialized, based on the

selection in PSDsoft

Configuration menu

Unchanged

All other registers

Cleared to 0

Unchanged

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