PSD834210MIT datasheet(48/89 Pages) STMICROELECTRONICS

48 / 89 page

PSD834F2V

48/89

For non-multiplexed 8-bit bus mode, address sig-

nals (A7-A0) are available to Port B in Address Out

Mode.

Note: Do not drive address signals with Address

Out Mode to an external memory device if it is in-

tended for the MCU to Boot from the external de-

vice. The MCU must first Boot from PSD memory

so the Direction and Control register bits can be

set.

Address In Mode

For MCUs that have more than 16 address sig-

nals, the higher addresses can be connected to

Port A, B, C, and D. The address input can be

latched in the Input Macrocell (IMC) by Address

Strobe (ALE/AS, PD0). Any input that is included

in the DPLD equations for the SRAM, or primary or

secondary Flash memory is considered to be an

address input.

Data Port Mode

Port A can be used as a data bus port for a MCU

with a non-multiplexed address/data bus. The

Data Port is connected to the data bus of the MCU.

The general I/O functions are disabled in Port A if

the port is configured as a Data Port.

Peripheral I/O Mode

Peripheral I/O mode can be used to interface with

external peripherals. In this mode, all of Port A

serves as a tri-state, bi-directional data buffer for

the MCU. Peripheral I/O Mode is enabled by set-

ting Bit 7 of the VM Register to a 1. Figure 24

shows how Port A acts as a bi-directional buffer for

the MCU data bus if Peripheral I/O Mode is en-

abled. An equation for PSEL0 and/or PSEL1 must

be written in PSDabel. The buffer is tri-stated

when PSEL0 or PSEL1 is not active.

JTAG In-System Programming (ISP)

Port C is JTAG compliant, and can be used for In-

System Programming (ISP). You can multiplex

JTAG operations with other functions on Port C

because In-System Programming (ISP) is not per-

formed in normal Operating mode. For more infor-

mation on the JTAG Port, see the section entitled

“Programming In-Circuit using the JTAG Serial In-

terface”, on page 61.

Port Configuration Registers (PCR)

Each Port has a set of Port Configuration Regis-

ters (PCR) used for configuration. The contents of

the registers can be accessed by the MCU through

normal read/write bus cycles at the addresses giv-

en in Table 6. The addresses in Table 6 are the off-

sets in hexadecimal from the base of the CSIOP

The pins of a port are individually configurable and

each bit in the register controls its respective pin.

For example, Bit 0 in a register refers to Bit 0 of its

port. The three Port Configuration Registers

(PCR), shown in Table 21, are used for setting the

Port configurations. The default Power-up state for

each register in Table 21 is 00h.

Table 21. Port Configuration Registers (PCR)

Note: 1. See Table 25 for Drive Register bit definition.

Control Register. Any bit reset to 0 in the Control

O Mode, and a 1 sets it to Address Out Mode. The

default mode is MCU I/O. Only Ports A and B have

an associated Control Register.

Figure 24. Peripheral I/O Mode

Port

MCU Access

Control

A,B

Write/Read

Direction

A,B,C,D

Write/Read

Drive Select1

A,B,C,D

Write/Read

PSEL0

PSEL1

PSEL

VM REGISTER BIT 7

PA0 - PA7

D0-D7

DATA BUS

AI02886

PSD834210MIT 数据表(PDF) 48 Page - STMicroelectronics

PSD834210MIT 数据表(HTML) 48 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89

数据表下载

链接网址

PSD834210MIT 数据表(PDF) 48 Page - STMicroelectronics

PSD834210MIT 数据表(HTML) 48 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89

数据表 下载

链接网址

数据表下载