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PSD834210MIT 数据表(PDF) 73 Page - STMicroelectronics |
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PSD834210MIT 数据表(HTML) 73 Page - STMicroelectronics |
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73 / 89 page  73/89 PSD834F2V Table 46. Input Macrocell Timing Note: 1. Inputs from Port A, B, and C relative to register/latch clock from the PLD. ALE latch timings refer to tAVLX and tLXAX . Figure 40. Input Macrocell Timing (product term clock) Symbol Parameter Conditions -10 -15 -20 PT Aloc Turbo Off Unit Min Max Min Max Min Max tIS Input Setup Time (Note 1) 000 ns tIH Input Hold Time (Note 1) 25 25 30 + 20 ns tINH NIB Input High Time (Note 1) 12 13 15 ns tINL NIB Input Low Time (Note 1) 12 13 15 ns tINO NIB Input to Combinatorial Delay (Note 1) 46 62 70 + 4 + 20 ns tINH tINL tINO tIH tIS PT CLOCK INPUT OUTPUT AI03101 |
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