PSD834210MIT datasheet(46/89 Pages) STMICROELECTRONICS

46 / 89 page

PSD834F2V

46/89

Table 18. Port Operating Modes

Note: 1. Can be multiplexed with other I/O functions.

Table 19. Port Operating Mode Settings

Note: 1. N/A = Not Applicable

2. The direction of the Port A,B,C, and D pins are controlled by the Direction Register ORed with the individual output enable product

term (.oe) from the CPLD AND Array.

3. Any of these three methods enables the JTAG pins on Port C.

Port Mode

Port A

Port B

Port C

Port D

MCU I/O

Yes

PLD I/O

McellAB Outputs

McellBC Outputs

Additional Ext. CS Outputs

PLD Inputs

Yes

Address Out

Yes (A7 – 0)

or (A15 – 8)

Address In

Yes

Data Port

Yes (D7 – 0)

Peripheral I/O

Yes

JTAG ISP

Yes1

Mode

Defined in

PSDabel

Defined in PSD

Configuration

Control

Setting

Direction

Setting

JTAG Enable

MCU I/O

Declare pins only

N/A1

1 = output,

0 = input

(Note 2)

N/A

PLD I/O

Logic equations

N/A

(Note 2)

N/A

Data Port (Port A)

N/A

Specify bus type

N/A

Address Out

(Port A,B)

Declare pins only

N/A

1 (Note 2)

N/A

Address In

(Port A,B,C,D)

Logic for equation

Input Macrocells

N/A

Peripheral I/O

(Port A)

Logic equations

(PSEL0 & 1)

N/A

PIO bit = 1

N/A

JTAG ISP (Note 3)

JTAGSEL

JTAG

Configuration

N/A

JTAG_Enable

PSD834210MIT 数据表(PDF) 46 Page - STMicroelectronics

PSD834210MIT 数据表(HTML) 46 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89

数据表下载